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Reconfigurable instruction set computing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/30
  • G06F-009/318
출원번호 US-0732392 (2003-12-09)
발명자 / 주소
  • Arnold, Jeffrey Mark
  • Banta, Gareld Howard
  • Johnson, Scott Daniel
  • Wang, Albert R.
출원인 / 주소
  • Stretch, Inc.
대리인 / 주소
    Carr &
인용정보 피인용 횟수 : 43  인용 특허 : 29

초록

A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the

대표청구항

1. A system for adding reconfigurable computational instructions to a computer, the system comprising:a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and at least one instruction extension; a first register file in the proces

이 특허에 인용된 특허 (29)

  1. Hunter Craig C. (Vancouver WA) Spohrer Thomas S. (Austin TX), CMOS implementation of a built-in self test input generator (BISTIG).
  2. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.
  3. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
  4. Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA), Distributed memory architecture for a configurable logic array and method for using distributed memory.
  5. DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
  6. Razdan Rahul (Princeton MA) Grundmann Bill (Westboro MA) Smith Michael D. (Belmont MA), Dynamically programmable reduced instruction set computer with programmable processor loading on program number field an.
  7. Razdan Rahul ; Smith Michael D., Hardware extraction technique for programmable reduced instruction set computers.
  8. Taylor Brad (Oakland CA), Implementation of a selected instruction set CPU in programmable hardware.
  9. Freidin Philip M. (Sunnyvale CA), Logic block with look-up table for configuration and memory.
  10. Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Logic system of logic networks with programmable selected functions and programmable operational controls.
  11. Cliff Richard G. (Santa Clara CA) Cope L. Todd (San Jose CA) Veenstra Kerry (Concord CA) Pedersen Bruce B. (Santa Clara CA), Look up table implementation of fast carry for adders and counters.
  12. Heybruck William F. (Charlotte NC), Method and apparatus for field testing field programmable logic arrays.
  13. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  14. Rupp, Charle' R., Multi-scale programmable array.
  15. Anderson Floyd E. (Round Rock TX) Lin Liang-Tsai (San Diego CA), On chip test system for configurable gate arrays.
  16. Turner John E. (Beaverton OR) Josephson Gregg R. (Lake Oswego OR), Programmable logic array.
  17. Cliff Richard G. ; Cope L. Todd ; Veenstra Kerry ; Pedersen Bruce B., Programmable logic array circuits comprising look up table implementation of fast carry adders and counters.
  18. Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Pedersen Bruce B. (Santa Clara CA) Veenstra Kerry (San Jose CA), Programmable logic array having local and long distance conductors.
  19. Cliff Richard G. (Milpitas CA) Ahanin Bahram (Cupertino CA), Programmable logic array integrated circuits with cascade connections between logic modules.
  20. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.
  21. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  22. Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.
  23. Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic element interconnections for programmable logic array integrated circuits.
  24. Mendel David W., Programmable logic integrated circuit architecture incorporating a global shareable expander.
  25. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
  26. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
  27. De Oliveira Kastrup Pereira, Bernardo; Bink, Adrianus J.; Hoogerbrugge, Jan, System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time.
  28. Veenstra Kerry S. (San Jose CA), Universal logic module with arithmetic capabilities.
  29. Freidin Philip M., Virtual high density programmable integrated circuit having addressable shared memory cells.

이 특허를 인용한 특허 (43)

  1. Ferren, Bran; Hillis, W. Daniel; Mangione Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Adjusting a processor operating parameter based on a performance criterion.
  2. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Alteration of execution of a program in response to an execution-optimization information.
  3. Wallach, Steven J.; Brewer, Tony, Compiler for generating an executable comprising instructions for a plurality of different instruction sets.
  4. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
  5. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Cross-architecture execution optimization.
  6. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Cross-architecture optimization.
  7. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
  8. Brokenshire, Daniel A.; O'Brien, John Kevin Patrick, Ensuring maximum code motion of accesses to DMA buffers.
  9. Rajendran, Resmi; Shastry, Pavan Venkata, Error recovery operations for a hardware accelerator.
  10. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Execution optimization using a processor resource management policy saved in an association with an instruction group.
  11. Mameri, Frederico A.; Fanning, Michael C., Extending a development environment.
  12. Johnson, Scott D., Extension adapter.
  13. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Handling processor computational errors.
  14. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T; Wood, Jr., Lowell L., Hardware-error tolerant computing.
  15. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
  16. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Instruction-associated processor resource optimization.
  17. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
  18. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
  19. Wallach, Steven J.; Brewer, Tony, Microprocessor architecture having alternative memory access paths.
  20. Hakewill, James Robert Howard; Fuhler, Richard A., Microprocessor architecture having extendible logic.
  21. Hakewill, James; Fuhler, Rich, Microprocessor architecture having extendible logic.
  22. Graham, Carl Norman; Jones, Simon; Lim, Seow Chuan; Nemouchi, Yazid; Wong, Kar-Lik; Aristodemou, Aris, Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline.
  23. Mangione-Smith, William Henry, Multi-votage synchronous systems.
  24. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  25. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  26. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  27. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  28. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Multiprocessor resource optimization.
  29. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Multiprocessor resource optimization.
  30. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Optimization of a hardware resource shared by a multiprocessor.
  31. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Optimization of instruction group execution through hardware resource management policies.
  32. Mangione-Smith, William Henry, Power consumption management.
  33. Mangione-Smith, William Henry, Power sparing synchronous apparatus.
  34. Mangione-Smith, William Henry, Power sparing synchronous apparatus.
  35. Ferren, Bran; Hillis, W. Daniel; Mangione-Smith, William Henry; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Predictive processor resource management.
  36. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Processor resource management.
  37. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
  38. Saito, Miyoshi; Fujisawa, Hisanori, Reconfigurable processor.
  39. Ferren, Bran; Hillis, W. Daniel; Myhrvold, Nathan P.; Tegreene, Clarence T.; Wood, Jr., Lowell L., Selecting a resource management policy for a resource available to a processor.
  40. Brewer, Tony, Systems and methods for mapping a neighborhood of data to general registers of a processing element.
  41. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
  42. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
  43. Mele, Jr., Joseph P.; Staab, Raymond R.; Logan, Robert G.; Fox, Anthony L., Universal multimedia engine and method for producing the same.
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