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A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element includes a voltage generator circuit providing the temperature dependent voltages, a first sampling switch and a second sampling switch. The voltage generator circuit includes a temperatu

A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element includes a voltage generator circuit providing the temperature dependent voltages, a first sampling switch and a second sampling switch. The voltage generator circuit includes a temperature sensing element being excited by a first switched current and a second switched current. The first and second sampling switches sample a first voltage and a second voltage at the temperature sensing element while the temperature sensing element is being excited by the second current and the first current, respectively. Each of the first and second sampling switches includes a boosted switch circuit incorporating a pedestal voltage compensation circuit. The sampled first and second voltages are coupled to be stored on capacitors external to the integrated circuit. The difference between the first voltage and the second voltage is measured to determine the temperature of the integrated circuit.

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1. A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element incorporated in the integrated circuit, the circuit comprising:a voltage generator circuit comprising:a first current source providing a first current;a second current source providing

1. A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element incorporated in the integrated circuit, the circuit comprising:a voltage generator circuit comprising:a first current source providing a first current;a second current source providing a second current, the first current and the second current having a fixed ratio;a temperature sensing element;a first current switch coupling the second current source to the temperature sensing element;a second current switch coupling the first current source to the temperature sensing element,wherein the first current switch and the second current switch are alternately asserted to alternately apply the first current and the second current to the temperature sensing element to generate the temperature dependent voltages;a first sampling switch coupling the voltage at the temperature sensing element to a first node, the first sampling switch comprising a self-bootstrapping constant on-resistance boosted switch circuit incorporating a pedestal voltage compensation circuit; anda second sampling switch coupling the voltage at the temperature sensing element to a second node, the second sampling switch comprising a self-bootstrapping constant on-resistance boosted switch circuit incorporating a pedestal voltage compensation circuit,wherein the first sampling switch samples the temperature dependent voltage of the temperature sensing element when the temperature sensing element is being excited by the second current and provides a first voltage indicative of the sampled voltage at the first node, and the second sampling switch samples the temperature dependent voltage of the temperature sensing element when the temperature sensing element is being excited by the first current and provides a second voltage indicative of the sampled voltage at the second node, whereby a difference between the first voltage and the second voltage is used to determine the temperature of the integrated circuit.2. The circuit of claim 1, wherein the first voltage is coupled to a first capacitor external to the integrated circuit and the second voltage is coupled to a second capacitor external to the integrated circuit so that the first capacitor is charged through the first sampling switch to the first voltage when the temperature sensing element is being excited by the second current and the second capacitor is charged through the second sampling switch to the second voltage when the temperature sensing element is being excited by the first current.3. The circuit of claim 2, wherein a voltage measurement device external to the integrated circuit is coupled to the first capacitor and the second capacitor for measuring a difference between the first voltage and the second voltage, the difference being indicative of the temperature of the integrated circuit.4. The circuit of claim 2, wherein the first current switch is controlled by a first clock signal for closing the switch during a first clock period and the second current switch is controlled by a second clock signal for closing the switch during a second clock period, and wherein the first sampling switch is enabled during the first clock period to charge the first capacitor and the second sampling switch is enabled during the second clock period to charge the second capacitor.5. The circuit of claim 4, wherein the first clock period and the second clock period are repeatedly applied to repeatedly excite the temperature sensing element, and the first sampling switch and the second sampling switch are accordingly repeatedly enabled to charge the first capacitor and the second capacitor.6. The circuit of claim 2, wherein the second capacitor has a smaller capacitance value than the first capacitor.7. The circuit of claim 1, wherein the second current is m times the first current where m comprises an integer or a fractional number.8. The circuit of claim 1, wherein the temperature sensing element is a diode-connected bipolar transistor.9. The circuit of claim 8, wherein the temperature of the integrated circuit is determined by T=(ΔVBE*q)/(nf*k*ln(I2/I1)), where ΔVBE is the difference between the first voltage and the second voltage, q is the electronic charge, k is the Boltzmann's constant, nf is the emission coefficient, I1 is the current value of the first current and I2 is the current value of the second current.10. The circuit of claim 3, wherein the integrated circuit comprises a temperature sensor, the integrated circuit including sensor circuitry for receiving the temperature dependent voltages at the temperature sensing element and generating a temperature output signal, and wherein the difference between the first voltage and the second voltage is used to determine a first temperature of the integrated circuit and the first temperature is compared with a second temperature generated by the temperature sensor as the temperature output signal, the difference between the first temperature and the second temperature being used to calibrate the temperature sensor.11. The circuit of claim 1, wherein the first sampling switch and the second sampling switch each comprises a boosted switch circuit, the boosted switch circuit comprising an input terminal coupled to the temperature sensing element and an output terminal coupled to the respective first or second node, the boosted switch circuit comprising:a switching device having an input node coupled to the input terminal and an output node coupled to the output terminal, the switching device having a control terminal;a charge storage device having a first terminal and a second terminal;a first switch coupled to the control terminal of the switching device, the first switch having a first position coupled to a third node and a second position being an open circuit;a second switch coupled to the first terminal of the charge storage device, the second switch having a first position coupled to a first reference voltage and a second position coupled to the control terminal of the switching device;a third switch coupled to the second terminal of the charge storage device, the third switch having a first position coupled to a second reference voltage and a second position coupled to the input terminal; anda pedestal voltage compensation circuit providing a compensating charge to the output terminal, the compensating charge being derived from a channel charge originated from the control terminal of the switching device when the switching device is turned off,wherein the first, second and third switches are in the first positions for turning off the boosted switch circuit when a first clock signal is deasserted and the first, second and third switches are in the second positions for turning on the boosted switch circuit when the first clock signal is asserted, and wherein the pedestal voltage compensation circuit provides the compensating charge to the output terminal when the boosted switch circuit is turned off.12. The circuit of claim 11, wherein the pedestal voltage compensation circuit in the boosted switch circuit comprises:a fourth switch coupled between the third node and a first supply voltage, the fourth switch having a first position being an open circuit and a second position coupling the third node to the first supply voltage; anda capacitor divider circuit coupled between the output terminal and the first supply voltage, a common node of the capacitor divider circuit being coupled to the third node,wherein the fourth switch is in the first position when the first sampling switch is turned off and the capacitor divider circuit generates a compensating charge at the output terminal based on the channel charge originated from the control terminal of the switching device when the boosted switch circuit is turned off.13. The circuit of claim 12, wherein the fourth switch in the pedestal voltage compensation circuit comprises:a fifth NMOS transistor having a first current handling terminal coupled to the third node, a second current handling terminal coupled to the first supply voltage, and a gate terminal driven by the first clock signal.14. The circuit of claim 12, wherein the capacitor divider circuit in the pedestal voltage compensation circuit comprises a first capacitor and a second capacitor connected in series between the output terminal and the first supply voltage, the common node of the first and second capacitors being the third node, the first and second capacitors dividing the channel charge from the control terminal of the switching device to generate the compensating charge.15. The circuit of claim 14, wherein the first capacitor and the second capacitor has equal capacitance.16. The circuit of claim 12, wherein the capacitor divider circuit in the pedestal voltage compensation circuit comprises a single capacitor connected between the output terminal and the third node, the single capacitor receiving and redirecting the entirety of the channel charge from the control terminal of the switching device as the compensating charge.17. The circuit of claim 11, wherein the switching device in the boosted switch circuit comprises an NMOS transistor.18. The circuit of claim 11, wherein the charge storage device in the boosted switch circuit is charged to a voltage value being the difference between the first precharge voltage and the second precharge voltage when said second and third switches are in the first positions.19. The circuit of claim 11, wherein the first supply voltage is a ground voltage.20. The circuit of claim 11, wherein the charge storage device in the boosted switch circuit comprises a MOS capacitor.21. The circuit of claim 11, wherein the switching device in the boosted switch circuit comprises a first NMOS transistor having a first current handling terminal coupled to the input terminal, a second current handling terminal coupled to the output terminal, and a gate terminal being the control terminal of said switching device.22. The circuit of claim 21, wherein the first switch comprises a second NMOS transistor having a first current handling terminal coupled to the gate terminal of the first NMOS transistor, a second current handling terminal coupled to the third node, and a gate terminal driven by an inverse of the first clock signal.23. The circuit of claim 21, wherein the second switch in the boosted switch circuit comprises:a first PMOS transistor having a first current handling terminal coupled to the first reference voltage, a second current handling terminal coupled to the first terminal of the charge storage device, and a gate terminal connected to the gate terminal of the first NMOS transistor; anda second PMOS transistor having a first current handling terminal coupled to the gate terminal of the first NMOS transistor, a second current handling terminal coupled to the first terminal of the charge storage device, and a gate terminal driven by an inverse of the first clock signal.24. The circuit of claim 21, wherein the third switch in the boosted switch circuit comprises:a third NMOS transistor having a first current handling terminal coupled to the second terminal of the charge storage device, a second current handling terminal coupled to the second reference voltage, and a gate terminal driven by an inverse of the first clock signal; anda fourth NMOS transistor having a first current handling terminal coupled to the input terminal, a second current handling terminal coupled to the first current handling terminal of the third NMOS transistor, and a gate terminal coupled to the gate terminal of the first NMOS transistor.25. The circuit of claim 11, wherein the boosted switch circuit further comprises a resistor network coupled between the output node of the switching device and the output terminal, the resistor network having an impedance value for matching the impedance value at the input terminal of the boosted switch circuit and having a temperature coefficient selected to maintain the impedance matching over the desired temperature range.26. The circuit of claim 11, wherein the boosted switch circuit further comprises a precharge voltage circuit for generating the first reference voltage and the second reference voltage, the precharge voltage circuit comprising:a third current source providing a third current, the third current having the same magnitude as the first current;a first resistor having a first terminal coupled to the third current source and a second terminal;a sixth NMOS transistor having a first current handling terminal coupled to the second terminal of the first resistor, a second current handling terminal and a control terminal coupled to the first terminal of the first resistor; anda temperature sensing element coupled between the second current handling terminal and the first supply voltage,wherein when the boosted switch circuit is used to implement the first sampling switch, the control terminal of the sixth NMOS transistor provides the first reference voltage and the second current handling terminal of the sixth NMOS transistor provides the second reference voltage; andwherein when the boosted switch circuit is used to implement the second sampling switch, the first current handling terminal of the sixth NMOS transistor provides the first reference voltage and the second current handling terminal of the sixth NMOS transistor provides the second reference voltage.27. The circuit of claim 11, wherein the boosted switch circuit further comprises a precharge voltage circuit for generating the first reference voltage and the second reference voltage, the precharge voltage circuit comprising:a third current source providing a third current, the third current having the same magnitude as the first current;a first resistor having a first terminal coupled to the third current source and a second terminal;a sixth NMOS transistor having a first current handling terminal coupled to the second terminal of the first resistor, a second current handling terminal and a control terminal coupled to the first terminal of the first resistor; anda temperature sensing element coupled between the second current handling terminal and the first supply voltage,wherein when the boosted switch circuit is used to implement the first sampling switch, the control terminal of the sixth NMOS transistor provides the first reference voltage and the second reference voltage comprises the first supply voltage; andwherein when the boosted switch circuit is used to implement the second sampling switch, the first current handling terminal of the sixth NMOS transistor provides the first reference voltage and the second reference voltage comprises the first supply voltage.