Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
출원번호
US-0446749
(2003-05-28)
발명자
/ 주소
Dubin, Valery M.
Cheng, Chin-Chang
Hussein, Makarem
Nguyen, Phi L.
Brain, Ruth A.
출원인 / 주소
Intel Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor &
인용정보
피인용 횟수 :
37인용 특허 :
27
초록▼
Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interc
Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
대표청구항▼
1. An interconnect structure comprising:a first interconnect line; a via including an electroless plug material over the first electroless material; a second interconnect line over the via; and a second electroless liner material disposed between the via and the second interconnect line, wherein a c
1. An interconnect structure comprising:a first interconnect line; a via including an electroless plug material over the first electroless material; a second interconnect line over the via; and a second electroless liner material disposed between the via and the second interconnect line, wherein a composition of the electroless plug material is different than a composition of the second electroless liner material. 2. The interconnect structure of claim 1, wherein the electroless plug material has a lesser total concentration of boron and phosphorous than the second electroless liner material.3. The interconnect structure of claim 2, wherein the electroless plug material and the second electroless liner material each comprise a cobalt-boron-phosphorous alloy.4. The interconnect structure of claim 2, wherein the electroless plug material has less than 10 atomic percent phosphorous and less than 5 atomic percent boron, and wherein the second electroless liner material has more than 10 atomic percent phosphorous and more than 5 atomic percent boron.5. The interconnect structure of claim 1, wherein at least one of the first electroless material, the electroless plug material, and the second electroless liner material comprises a cobolt-boron-phosphorous alloy.6. The interconnect structure of claim 5, wherein the alloy comprises between 1-10 atomic percent (at%) boron, between 1-20 at% phosphorous, and between 70-98 at% cobalt.7. The interconnect structure of claim 1 wherein the first interconnect line in recessed in a dielectric material, and wherein the first electroless material includes material that is inlaid in the recessed first interconnect line.8. The interconnect structure of claim 1, wherein the via plug comprises an unlanded via plug.9. The interconnect structure of claim 1, implemented in a computer system comprising a communication device.10. An interconnect structure comprising:a dielectric material; an interconnect line recessed in the dielectric material; an unlaid electroless material over the recessed interconnect line; and un unlanded via having a first portion over the inlaid electroless material and a second portion adjacent to the interconnect line and below the inlaid electroless material. 11. The interconnect structure of claim 10, wherein a surface of the inlaid electroless material is planar with a surface of the dielectric material.12. The interconnect structure of claim 10, wherein the inlaid electroless material comprises a cobalt-boron-phosphorous alloy.13. The interconnect structure of claim 12, wherein the alloy comprises between 1-10 atomic percent (at%) boron, between 1-20 at phosphorous, and between 70-98 at% cobalt.14. The interconnect structure of claim 10, implemented in a computer system comprising a communication device.15. An interconnect structure comprising:an interconnect line; an electroless material over the interconnect line, the electroless material including a cobalt-boron- phosphorous alloy; and an unlanded via having a first portion over the electroless material and a second portion adjacent to the interconnect line and below the electroless material. 16. The interconnect structure of claim 15, wherein the alloy comprises between 1-10 atomic percent (at%) boron, between 1-20 at% phosphorous, and between 70-98 at% cobalt.17. The interconnect structure of claim 15, wherein the interconnect line is recessed in a dielectric material, and wherein the electroless material includes material that is inlaid in the recessed interconnect line.18. The interconnect structure of claim 17, wherein a surface of the electroless material is planar with a surface of the dielectric material.19. The interconnect structure of claim 15, implemented in a computer system comprising a communication device.
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이 특허에 인용된 특허 (27)
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Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
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Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
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Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
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Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same.
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