IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0037609
(2002-01-02)
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발명자
/ 주소 |
- Hepler, Edward L.
- Starsinic, Michael F.
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출원인 / 주소 |
- Interdigital Technology Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
5 인용 특허 :
14 |
초록
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The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.
대표청구항
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1. A method employed by a decoder for calculating forward and reverse metrics required for performing an output calculation to accurately determine binary states of received signals, comprising the steps of:(a) performing the forward metric calculations in two stages, wherein a first group of the fo
1. A method employed by a decoder for calculating forward and reverse metrics required for performing an output calculation to accurately determine binary states of received signals, comprising the steps of:(a) performing the forward metric calculations in two stages, wherein a first group of the forward metric calculations are calculated in a first stage followed by a second group of forward metric calculations being calculated in a second stage; (b) storing the metric calculations obtained in step (a) in a memory; (c) reading the forward metrics calculated during the first stage from the memory for use with reverse metric values to perform the an output calculation; (d) performing the reverse metric calculations in the second stage, following the first stage; (e) performing a second half of forward metric calculations as said reverse calculations are being performed; and (f) storing each of the forward metric calculations performed in the second stage into a memory location of said memory that a forward metric calculated during the first stage is being read out for use in an output calculation. 2. The method of claim 1 further comprising the step of performing output calculations utilizing the forward metrics calculated in the first stage and the reverse metrics calculated in the second stage.3. The method of claim 1 wherein step (f) is performed employing a common clock edge of a clock signal.4. The method of claim 2 further comprising performing reverse metrics in a third stage following said second stage for use with the forward metrics calculated in the second stage for performing output calculations utilizing the forward metrics calculated during the second stage and the reverse metrics calculated during the third stage.5. A method employed by a decoder for decoding a transmission received from a remote location which includes data bits and associated parity bits, comprising the steps of;(a) calculating, during a first time interval, a forward metric value for each data bit and its accompanying parity bits received from a transmission location; (b) storing each forward metric value in a first memory; (c) storing each received data bit and accompanying parity bits in a local memory as they are received; (d) reading out a forward metric value from the first memory during a second time interval for calculating an extrinsic value; (e) utilizing the data bit and associated parity bits previously stored in memory for calculating a reverse metric value during said second time interval; and (f) during said second time interval, calculating a forward metric value for data bits and associated parity bits received during the second time interval and storing each forward metric value calculated during the second time interval in a memory location of said first memory from which a forward metric value is read out during step (d). 6. The method of claim 5 wherein the data bit and associated parity bits read into the local memory during step (c) are read out of the local memory in reverse order for use in calculating the reverse metrics.7. The method of claim 5 wherein the calculated forward metric values are read out of memory in reverse of the order in which the forward metric values are read into memory for use in calculating the extrinsic value.8. The method of claim 5 wherein step (a) further comprises performing a gamma calculation on said data bit and associated parity bits prior to calculating a forward metric value during said first time interval.9. The method of claim 5 further comprising calculating an initial extrinsic value based on a given forward metric value, a given reverse metric value and a given data bit associated parity bit.10. The method of claim 9 wherein the extrinsic value is stored in an extrinsic memory.11. The method of claim 10 further comprising the step of extracting the data bit and associated parity bits from the local memory; and performing a gamma calculation on the data bit and associated parity bits during the second time interval for use in the extrinsic value calculation.12. The method of claim 11 further comprising subtracting a data bit and associated parity bits read out of the local memory during the second time interval from the initial extrinsic value to obtain a final extrinsic value.13. The method of claim 11 further comprising determining a binary state of the output data of the extrinsic value calculator to make a hard decision regarding the binary state; andstoring the hard decision output in a memory. 14. The method of claim 9 wherein the step of storing the extrinsic value includes storing the intrinsic value in a memory location linked with the data bit utilized to calculate the extrinsic value being stored.15. A method employed by a turbo decoder receiving data bits each accompanied by associated parity bits, comprising the steps of:(a) performing forward metric calculations in two successive time intervals wherein one group of forward metric calculations are calculated in a first time interval followed by a second time interval; (b) storing each of the forward metric calculations performed during the first interval in a memory; (c) reading each forward metric value calculated during the first time interval from said memory for use together with a reverse metric value in calculating an extrinsic value; (d) performing reverse metric calculations, during the second time interval and after completion of the forward metric calculations performed during the first time interval; and (e) writing each forward metric value calculated during the second time interval into a memory location in said memory from which a forward metric value calculated during the first time interval is read out of memory. 16. A turbo decoder for calculating forward and reverse metrics required for performing a calculation to determine binary states of received signals comprising the method steps of:(a) generating a memory location in an extrinsic memory; (b) receiving signals comprising data bits and associated parity bits which may be corrupted by noise or the like; (c) storing the data bit, associated parity bits, a memory location and a starting extrinsic value; (d) calculating a first set of forward metric values based on said data bit, associated parity bits and starting extrinsic value; (e) storing the forward metric value calculated into a forward metric memory; (f) reading the calculated forward metric value from memory for use together with a reverse metric value in calculation of an extrinsic value; (g) employing steps (a)-(c) for calculating a second set of forward metric values while the reverse metric values are being calculated; and (h) storing each of the second set of forward metric values in a memory location which is the same one in which one of the first set of forward metric values is read out for use in calculation of a reverse metric value. 17. The method of claim 16 further comprising;reading the forward metric values out of memory in reverse order from which they were read into memory for calculation of reverse metric values. 18. A turbo decoder for calculating forward metrics (α) and reverse (β) metrics required for performing a calculation to determine binary states of received signals comprising the method steps of:(a) receiving signals comprising data bits each having associated parity bits, which signals may be corrupted by noise or the like; (b) generating a memory location in an extrinsic memory for storing an extrinsic value; (c) storing a first data bit, associated parity bits, memory location and a starting extrinsic value in a first memory; (d) calculating a first forward metric value based on said data bit, associated parity bits and starting extrinsic value; (e) storing the forward metric value calculated in a forward metric memory; (f) reading the calculated forward metric value from the forward metric memory for use together with a reverse metric in calculating an extrinsic value; (g) employing steps (a)-(c) for calculating a first forward metric value of a second set of forward metric values while the reverse metric value is being calculated; and (h) storing the first forward metric value of the second set of forward metric values in the same memory location as one in which one of the first set of forward metric values is read out for use in calculation of an extrinsic value. 19. A turbo decoder for calculating forward and reverse metrics required for performing a calculation to determine binary states of received signals comprising:an extrinsic memory; first means for generating a memory location in the extrinsic memory; second means for receiving signals comprising data bits each having associated parity bits which may be corrupted by noise or the like; third means for storing the data bit, associated parity bits and memory location; fourth means for calculating a first set of forward metric values based on said data bit, associated parity bits and an initial starting extrinsic value; fifth means for storing the forward metric calculated in a forward metric memory; sixth means for reading the calculated forward metric from said forward metric memory for use, together with a reverse metric, in calculating an extrinsic value; said first, second and third means calculating a second set of forward metric values while the reverse metric values are being calculated; and said fifth means including means for storing one of the second set of forward metric values in the same memory location of the forward metric memory as one in which one of the first set of forward metric values is read out for use in calculation of an extrinsic value. 20. A storing method for use in a turbo decoder for calculating forward and reverse metrics required for performing a calculation to determine binary states of received signals comprising the steps of:(a) storing a first group of forward metric values in said memory in a given order; (b) reading out stored metric values in an order of last calculated to first calculated; and (c) storing a second group of forward metric values in a given order, whereby a first calculated forward metric value of said second group is stored in a memory location from which the last calculated metric value of said second group is read out. 21. The storing technique of claim 20 further comprising: calculating a reverse metric value based on the forward metric value read out of memory.22. Apparatus for use in a turbo decoder for calculating forward and reverse metrics required for performing a calculation to determine binary states of received signals comprising:a first memory for storing a data bit and associated parity bits; a forward metric memory; means for calculating a first group of forward metric values based on said data bit and associated parity bits; means for storing said first group of forward metric values in said memory in a given order; means for reading out the first group of stored metric values from said memory in an order of last calculated to first calculated; means for controlling said means for calculating to calculate a second group of forward metric values following calculation of said first group of metric values; and means for storing the second group of forward metric values in a given order in said forward metric memory, whereby a first calculated forward metric value of said second group is stored in a memory location in which the last calculated metric value of said first group is read out. 23. The apparatus of claim 22 further comprising:second means for calculating, during calculation of said first group of forward metric values, a reverse metric value based on the data bit and associated parity bits read out of said first memory. 24. A method employed by a decoder for calculating forward and reverse metrics required for performing an output calculation to determine binary states of received signals, comprising the steps of:(a) performing the reverse metric calculations in two stages, wherein one group of reverse metric calculations are calculated in a first stage followed by a second group of reverse metric calculations being calculated in a second stage; (b) storing each of the reverse metric calculations performed in the first stage; (c) reading the reverse metric values calculated during the first stage from memory for use in the output calculation; (d) performing the forward metric calculations after completion of the first stage of reverse metric calculations and before the second stage of reverse metric calculations; and (e) writing each reverse metric calculated during the second stage into a memory location that a reverse metric calculated during the first stage is being read out for use in an output calculation. 25. The method of claim 24 further comprising the step of performing output calculations utilizing the reverse metrics calculated in the first stage and the forward metrics calculated in the second stage.26. The method of claim 24 wherein steps (c) and (e) are performed employing a common clock edge of a clock signal.27. The method of claim 25 further comprising performing forward metrics in a third stage following said second stage responsive to the reverse metrics calculated in the second stage; andperforming output calculations utilizing the reverse metric values calculated during the second stage and the forward metric values calculated during the third stage. 28. A method employed by a decoder for decoding a transmission received from a remote location which includes data bits and associated parity bits, comprising the steps of:(a) calculating, during a first time interval, a reverse metric value for each data bit and its accompanying parity bits received from a transmission location; (b) storing each reverse metric value in a first memory; (c) storing each received data bit and accompanying parity bits in a local memory as they are received; (d) reading out a reverse metric value from the first memory for use in calculating an extrinsic value; (e) utilizing the data bit and associated parity bits previously stored in the local memory for calculating a forward metric value; and (f) during a second time interval, calculating a reverse metric value for data bits and associated parity bits received during the second time interval and storing each reverse metric value calculated during the second time interval in a memory location of the first memory in which a reverse metric value is read out during step (d). 29. The method of claim 28 wherein the data bit and associated parity bits read into the local memory during step (c) are read out of the local memory in reverse order for use in calculating the extrinsic value.30. The method of claim 29 wherein the reverse metric values calculated in the first time interval are read out of memory in reverse of the order in which the reverse metric values calculated in the second time interval are read into memory.31. The method of claim 29 further comprising calculating an extrinsic value based on a given forward metric value, a given reverse metric value and a given data bit and associated parity bits.32. A method employed by a decoder for calculating forward and reverse metrics required for performing calculations to determine binary states of received signals, comprising:(a) performing a first group of forward metric calculations during a first stage; (b) storing the first group of forward metric values in a memory; (c) performing reverse metric calculations during a second stage following said first stage; (d) performing a second group of forward metric calculations as reverse metric values are calculated during the second stage; (e) reading forward metric values of said first group out of locations in memory for use with the reverse metric values calculated during said second stage for performing calculations to determine binary states of said received signals; and (f) storing calculations of said second group of forward metric values during a time that the reverse metric values are being calculated in the second stage, whereby each forward metric value calculated during the second stage is stored in the same location that a forward metric value calculated during the first stage is being read out for use in performing calculations to determine binary states of said received signals. 33. Apparatus for calculating forward and reverse metrics required for performing an output calculation to determine binary states of received signals, comprising:means for performing the reverse metric calculations in two stages, wherein one group of reverse metric calculations are calculated in a first stage followed by a second group of reverse metric calculations being calculated in a second stage; means for storing each of the reverse metric calculations performed in the first stage; means for reading the reverse metric values calculated during the first stage from memory for use in the output calculation; means for performing the forward metric calculations after completion of the first stage of reverse metric calculations and before the second stage of reverse metric calculations; and means for writing each reverse metric calculated during the second stage into a memory location that a reverse metric calculated during the first stage is being read out for use in an output calculation. 34. The apparatus of claim 33 further comprising means for performing output calculations utilizing the reverse metrics calculated in the first stage and the forward metrics calculated in the second stage.35. The apparatus of claim 33 further comprising means for performing forward metrics in a third stage following said second stage responsive to the reverse metrics calculated in the second stage; andmeans for performing output calculations utilizing the reverse metric values calculated during the second stage and the forward metric values calculated during the third stage. 36. Apparatus for decoding a transmission received from a remote location which includes data bits and associated parity bits, comprising:means for calculating, during a first time interval, a reverse metric value for each data bit and its accompanying parity bits received from a transmission location; a first memory for storing each reverse metric value; a local memory for storing each received data bit and accompanying parity bits; means for reading out a reverse metric value from the first memory for use in calculating an extrinsic value; means for utilizing the data bit and associated parity bits previously stored in the local memory for calculating a forward metric; and means, during a second time interval, for calculating a reverse metric value for data bits and associated parity bits received during the second time interval and storing each reverse metric value calculated during the second time interval in a memory location of the first memory in which a reverse metric value is read out during step (d). 37. Apparatus of claim 36 including means for reading out of the local memory the data bit and associated parity bits read into the local memory in reverse order for use in calculating the extrinsic value by read-only means.38. The apparatus of claim 37 further comprising means for calculating an extrinsic value based on a given forward metric value, a given reverse metric value and a given data bit and associated parity bits.39. Apparatus for calculating forward and reverse metrics required for performing calculations to determine binary states of received signals, comprising:means for performing a first group of forward metric calculations during a first stage; memory means for storing the first group of forward metric values; means for performing reverse metric calculations during a second stage following said first stage; means for performing a second group of forward metric calculations as reverse metric values are calculated during the second stage; means for reading forward metric values of said first group out of locations in said memory means for use with the reverse metric values calculated during said second stage for performing calculations to determine binary states of said received signals; and means for storing calculations of said second group of forward metric values during a time that the reverse metric values are being calculated in the second stage, whereby each forward metric value calculated during the second stage is stored in the same location in said memory means that a forward metric value calculated during the first stage is being read out for use in performing calculations to determine binary stages of said received signals.
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