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Treatment method of film quality for the manufacture of substrates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/46
  • H01L-021/11
  • H01L-021/311
출원번호 US-0710628 (2000-11-08)
발명자 / 주소
  • Kang, Sien G.
  • Malik, Igor J.
출원인 / 주소
  • Silicon Genesis Corporation
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 59  인용 특허 : 41

초록

A method of fabricating substrates, e.g., bulk wafers, silicon on insulator wafers, silicon on saphire, optoelectronic substrates. The method includes providing a substrate (e.g., silicon, gallium arsenide, gallium nitride, quartz). The substrate has a film characterized by a non-uniform surface, wh

대표청구항

1. A method of fabricating substrates, the method comprising:providing a substrate comprising a film of material characterized by a non-uniform surface, the non-uniform surface including a plurality of defects, at least some of the defects being of a size ranging from about 100 Angstroms and greater

이 특허에 인용된 특허 (41)

  1. Matsushita Takeshi,JPX ; Morita Etsuo,JPX ; Nakajima Tsuneo,JPX ; Hasegawa Hiroyuki,JPX ; Shingyouji Takayuki,JPX, A SOI substrate fabricating method.
  2. Walsh Robert J. (Ballwin MO), Apparatus for processing semiconductor wafers.
  3. Henley Francois J. ; Cheung Nathan W., Controlled cleavage process and resulting device using beta annealing.
  4. Drobny Vladimir F. ; Bao Kevin X., Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects.
  5. Gonzalez Fernando ; Thakur Randhir P.S., In situ rapid thermal etch and rapid thermal oxidation.
  6. Hirayama Hideo (Yokohama JPX) Ibaraki Nobuki (Kanagawa-ken JPX) Hidaka Koji (Yokohama JPX) Mizouchi Kiyotsugu (Yokohama JPX) Kobayashi Michiya (Yokohama JPX) Ishigami Takashi (Yokohama JPX) Sakai Ryo, Light-shielding film, useable in an LCD, in which fine particles of a metal or semi-metal are dispersed in and throughou.
  7. Sato Nobuhiko,JPX, Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same.
  8. Ohta Yutaka (Gunma JPX) Nakano Masatake (Gunma JPX) Katayama Masatake (Gunma JPX) Abe Takao (Gunma JPX), Method and apparatus for production of extremely thin SOI film substrate.
  9. Rolfson J. Brett ; Lowrey Tyler A. ; Gonzalez Fernando ; Barbour W. Richard, Method for CMOS well drive in a non-inert ambient.
  10. Cathey David A. (Boise ID), Method for etching high aspect ratio features.
  11. Jastrzebski Lubomir L. (Plainsboro NJ) Ipri Alfred C. (Princeton NJ) Kokkas Achilles G. (Plainsboro NJ), Method for fabricating a self-aligned vertical IGFET.
  12. Zhong Lei,JPX ; Shimoi Norihiro,JPX ; Kirino Yoshio,JPX, Method for making a slant-surface silicon wafer having a reconstructed atomic-level stepped surface structure.
  13. Tayanaka Hiroshi,JPX, Method for making thin film semiconductor.
  14. Bruel Michel (Veurey FRX), Method for placing semiconductive plates on a support.
  15. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  16. Habuka Hitoshi,JPX ; Otsuka Toru,JPX ; Katayama Masatake,JPX, Method for smoothing surface of silicon single crystal substrate.
  17. Goesele Ulrich M. ; Tong Q.-Y., Method for the transfer of thin layers of monocrystalline material to a desirable substrate.
  18. Horai Masataka (Saga JPX) Adachi Naoshi (Saga JPX) Nishikawa Hideshi (Saga JPX) Sano Masakazu (Saga JPX), Method of annealing a semiconductor wafer in a hydrogen atmosphere to desorb surface contaminants.
  19. MacLeish Joseph H. ; Sanganeria Mahesh K., Method of cleaning wafer substrates.
  20. Takizawa Ritsuo (Tokyo JPX), Method of making a semiconductor device having a process of hydrogen annealing.
  21. Li Jianming (Beijing CNX), Method of making silicon material with enhanced surface mobility by hydrogen ion implantation.
  22. Ritsuo Takizawa JP, Method of manufacturing semiconductor substrate and method of manufacturing solid-state image-pickup device.
  23. Foresi James S. ; Agarwal Anu M. ; Black Marcie R. ; Koker Debra M. ; Kimerling Lionel C., Methods of forming polycrystalline semiconductor waveguides for optoelectronic integrated circuits, and devices formed t.
  24. Scudder Lance (Mountain View CA) Riley Norma (Pleasanton CA), Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer.
  25. Pinker Ronald D. (Peekskill NY) Merchant Steven L. (Yorktown Heights NY) Arnold ; Emil (Chappaqua NY), Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning.
  26. Menigaux Louis (Bures sur Yvett FRX) Bruno Adrien (Palaiseau FRX), Process for producing a structure integrating a cleaved optical guide with an optical fibre support for a guide-fibre op.
  27. Kato Takashi (Kawasaki JPX) Toyokura Nobuo (Kawasaki JPX), Process for producing dielectric layers for semiconductor devices.
  28. Sakaguchi Kiyofumi,JPX ; Yonehara Takao,JPX, Process for producing semiconductor article.
  29. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Process for producing semiconductor substrate by heating to flatten an unpolished surface.
  30. Bruel Michel,FRX, Process for the manufacture of thin films of semiconductor material.
  31. Bruel Michel (Veurey FRX), Process for the production of a relief structure on a semiconductor material support.
  32. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  33. Gonzalez Fernando ; Thakur Randhir P. S., Rapid thermal etch and rapid thermal oxidation.
  34. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Semiconductor substrate and method of manufacturing the same.
  35. Matsushita Takeshi,JPX ; Kusunoki Misao,JPX ; Tatsumi Takaaki,JPX, Semiconductor substrate and thin film semiconductor device, method of manufacturing the same, and anodizing apparatus.
  36. Ohshima Hisayoshi,JPX ; Matsui Masaki,JPX ; Onoda Kunihiro,JPX ; Yamauchi Shoichi,JPX, Semiconductor substrate manufacturing method.
  37. Benton Janet L. (Warren NJ) Jindal Renuka P. (Berkeley Heights NJ) Xie Ya-Hong (Flemington NJ), Silicon photodiode for monolithic integrated circuits and method for making same.
  38. Malik Igor J. ; Kang Sien G., Smoothing method for cleaved films made using thermal treatment.
  39. Kang Sien G. ; Malik Igor J., Surface finishing of SOI substrates using an EPI process.
  40. Yoneda Kiyoshi (Hirakata JPX) Mameno Kazunobu (Kyoto JPX) Kawahara Keita (Nagaokakyo JPX) Inoue Yasunori (Osaka JPX), Surface smoothing method and method of forming SOI substrate using the surface smoothing method.
  41. Kang Sien G. ; Malik Igor J., Treatment method of cleaved film for the manufacture of substrates.

이 특허를 인용한 특허 (59)

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  2. Clausen, William J.; Furino, Jr., James P.; Yore, Michael D., Body-biased switching device.
  3. Nohra, George, Body-contacted partially depleted silicon on insulator transistor.
  4. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
  5. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
  6. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
  7. Gulari, Levent, Contoured insulator layer of silicon-on-insulator wafers and process of manufacture.
  8. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  9. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  10. Blake, Julian G.; Murphy, Paul J., Cooled cleaving implant.
  11. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  12. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  13. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
  14. Letertre, Fabrice; Ghyselen, Bruno; Rayssac, Olivier, Fabrication of substrates with a useful layer of monocrystalline semiconductor material.
  15. Letertre, Fabrice; Ghyselen, Bruno; Rayssac, Olivier, Fabrication of substrates with a useful layer of monocrystalline semiconductor material.
  16. Nohra, George, Field effect transistor switching circuit.
  17. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
  18. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  19. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  20. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  21. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  22. Henley, Francois J., Layer transfer of films utilizing controlled propagation.
  23. Henley, Francois J., Layer transfer of films utilizing controlled shear region.
  24. Samoilov, Arkadii, Low temperature etchant for treatment of silicon-containing surfaces.
  25. Samoilov,Arkadii V., Low temperature etchant for treatment of silicon-containing surfaces.
  26. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
  27. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  28. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  29. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  30. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  31. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  32. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  33. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  34. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  35. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  36. Henley,Francois J.; Cheung,Nathan, Method and device for controlled cleaving process.
  37. Henley, Francois J., Method and structure for fabricating solar cells using a thick layer transfer process.
  38. Henley, Francois J., Method of cleaving a thin sapphire layer from a bulk material by implanting a plurality of particles and performing a controlled cleaving process.
  39. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
  40. Kim, Yihwan; Samoilov, Arkadii V., Methods of selective deposition of heavily doped epitaxial SiGe.
  41. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
  42. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
  43. Henley, Francois J.; Brailove, Adam, Race track configuration and method for wafering silicon solar substrates.
  44. Clausen, William J.; Furino, Jr., James P., Radio frequency switch device with source-follower.
  45. Akiyama, Shoji, SOS substrate with reduced stress.
  46. Olson, Chris, Semiconductor devices with switchable ground-body connection.
  47. Sinha, Nishant; Sandhu, Gurtej S.; Smythe, John, Semiconductor material manufacture.
  48. Carroll, Michael; Kerr, Daniel Charles; Iversen, Christian Rye; Mason, Philip; Costa, Julio; Spears, Edward T., Semiconductor radio frequency switch with body contact.
  49. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  50. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  51. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  52. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  53. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  54. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  55. Ravindran, Arjun; Furino, Jr., James P., Switching device with diode-biased field-effect transistor (FET).
  56. Connick, Richard; Ravindran, Arjun, Switching device with negative bias circuit.
  57. Yang, Xiaomin; Furino, Jr., James P., Switching device with non-negative biasing.
  58. Prabhakar, III, Ravishankar; Furino, Jr., James P., Switching device with resistive divider.
  59. Brailove, Adam; Liu, Zuqin; Henley, Francois J.; Lamm, Albert J., Techniques for forming thin films by implantation with reduced channeling.
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