$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0632550 (2003-08-02)
발명자 / 주소
  • Karnezos, Marcos
출원인 / 주소
  • ChipPAC, Inc.
대리인 / 주소
    Haynes Beffel &
인용정보 피인용 횟수 : 77  인용 특허 : 32

초록

A semiconductor multi-package module having stacked first and second packages, each package including a die attached to a substrate, in which the first and second substrates are interconnected by wire bonding, and wherein at least one said package comprises a stacked die package. Also, a method for

대표청구항

1. A multi-package module comprising stacked lower and upper packages, the lower package including a die attached to and electrically connected to a lower substrate and the upper package including a die attached to and electrically connected to an upper substrate, wherein the upper and lower substra

이 특허에 인용된 특허 (32) 인용/피인용 타임라인 분석

  1. Makoto Terui JP, BGA package and method for fabricating the same.
  2. Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.
  3. Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.
  4. Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.
  5. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
  6. Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.
  7. Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.
  8. Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.
  9. Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.
  10. Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.
  11. Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.
  12. Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.
  13. Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.
  14. Ichikawa, Sunji, Semiconductor device.
  15. Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.
  16. Tadashi Komiyama JP, Semiconductor device.
  17. Terui, Makoto, Semiconductor device.
  18. Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.
  19. Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.
  20. Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
  21. Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.
  22. Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.
  23. Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.
  24. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
  25. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.
  26. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.
  27. Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.
  28. Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
  29. Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
  30. Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
  31. Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.
  32. Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.

이 특허를 인용한 특허 (77) 인용/피인용 타임라인 분석

  1. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan, Adhesive/spacer island structure for multiple die package.
  2. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan; Karnezos, Marcos, Adhesive/spacer island structure for stacking over wire bonded die.
  3. Kang, Tae Min, Chip stack package utilizing a dummy pattern die between stacked chips for reducing package size.
  4. Gehman,John; Christensen,Brian H.; Kleffner,James H.; Mistry,Addi B.; Patten,David; Rohde,John; Wilde,Daryl, Digital and RF system and method therefor.
  5. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Encapsulant cavity integrated circuit package system and method of fabrication thereof.
  6. Thomas, John; Rapport, Russell; Washburn, Robert, Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area.
  7. Yim,Choong Bin; Kwon,Hyeog Chan; Ha,Jong Woo, Integrated circuit package system.
  8. Park, Soo-San; Kwon, Hyeog Chan; Lee, Sang-Ho; Ha, Jong-Woo, Integrated circuit package system including stacked die.
  9. Park,Soo San; Kwon,Hyeog Chan; Lee,Sang Ho; Ha,Jong Woo, Integrated circuit package system including stacked die.
  10. Pendse, Rajendra D., Integrated circuit package system including zero fillet resin.
  11. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit package system with an encapsulant cavity and method of fabrication thereof.
  12. Camacho, Zigmund Ramirez; Bathan, Henry D.; Trasporto, Arnel; Punzalan, Jeffrey D., Integrated circuit package system with die on base package.
  13. Chow, Seng Guan; Shim, II Kwon; Han, Byung Joon, Integrated circuit package system with exposed interconnects.
  14. Camacho, Zigmund Ramirez; Bathan, Henry D.; Trasporto, Arnel; Punzalan, Jeffrey D., Integrated circuit package system with laminate base.
  15. Camacho, Zigmund Ramirez; Bathan, Henry D.; Trasporto, Arnel; Punzalan, Jeffrey D., Integrated circuit package system with laminate base.
  16. Yee, Jae Hak; Myung, Junwoo; Jang, Byoung Wook, Integrated circuit package system with stacked die.
  17. Yim, Choong Bin; Kwon, Hyeog Chan; Ha, Jong-Woo, Integrated circuit package-in-package system.
  18. Yim,Choong Bin; Kwon,Hyeog Chan; Ha,Jong Woo, Integrated circuit package-in-package system.
  19. Yim, Choong Bin; Kwon, Hyeog Chan; Ha, Jong-Woo, Integrated circuit package-in-package system and method for making thereof.
  20. Ha, Jong-Woo; Hong, BumJoon; Lee, Sang-Ho; Park, Soo-San, Integrated circuit package-in-package system with carrier interposer.
  21. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof.
  22. Yim, Choong Bin; Kwon, Hyeog Chan; Ha, Jong-Woo, Integrated circuit packaging system with carrier and method of manufacture thereof.
  23. Do, Byung Tai; Huang, Rui; Pagaila, Reza Argenty, Integrated circuit packaging system with package stacking and method of manufacture thereof.
  24. Kim, Geun Sik, Integrated circuit packaging system with package stacking and method of manufacture thereof.
  25. Yamano,Takaharu, Laminated semiconductor package.
  26. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  27. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  28. Wehrly, Jr., James Douglas, Memory card and method for devising.
  29. Wehrly, Jr., James Douglas, Memory card and method for devising.
  30. Camerlo,Sergio; Zou,Yida; Cafiero,Luca; Myers,Gary L.; Parizi,Bobby; Liang,Hsing Sheng, Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate.
  31. Karnezos,Marcos; Carson,Flynn, Method for making a semiconductor multi-package module having inverted bump chip carrier second package.
  32. Karnezos,Marcos, Method for making semiconductor multi-package module having inverted second package and including additional die or package stacked on second package.
  33. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  34. Karnezos,Marcos, Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides.
  35. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.
  36. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate.
  37. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
  38. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
  39. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA).
  40. Karnezos, Marcos, Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages.
  41. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.
  42. Karnezos,Marcos, Method of fabricating a semiconductor stacked multi-package module having inverted second package.
  43. Karnezos, Marcos, Method of fabricating module having stacked chip scale semiconductor packages.
  44. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  45. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  46. Karnezos,Marcos, Module having stacked chip scale semiconductor packages.
  47. Ha, Jong-Woo; Lee, SeongMin; Bae, JoHyun, Mountable integrated circuit package-in-package system with adhesive spacing structures.
  48. Chow, Seng Guan; Kuan, Heap Hoe, Multi-chip package system.
  49. Karnezos, Marcos, Multiple chip package module having inverted package stacked over die.
  50. Karnezos, Marcos, Multiple chip package module including die stacked over encapsulated package.
  51. Woodyard, Jon T., Package in package (PiP).
  52. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  53. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
  54. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
  55. Kim,Jae Hong; Kim,Heui Seog; Sin,Wha Su; Jeon,Jong Keun, Package stack and manufacturing method thereof.
  56. Karnezos,Marcos; Shim,IL Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides.
  57. Imoto,Takashi; Takubo,Chiaki, Semiconductor device and manufacturing method therefor.
  58. Park, Yeonglm; Chi, HeeJo; Lee, HyungMin, Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer.
  59. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  60. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  61. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  62. Karnezos,Marcos; Carson,Flynn; Kim,Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
  63. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  64. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  65. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  66. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  67. Karnezos,Marcos; Carson,Flynn, Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides.
  68. Karnezos,Marcos; Shim,Il Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides.
  69. Szewerenko,Leland; Goodwin,Paul; Wehrly, Jr.,James Douglas, Stackable micropackages and stacked modules.
  70. Wehrly, Jr.,James Douglas, Stacked integrated circuit module.
  71. Carson, Flynn, Stacked integrated circuit package system and method of manufacture therefor.
  72. Ha,Jong Woo; Kim, Jr.,Gwang; Park,Ju Hyun, Stacked integrated circuit package-in-package system.
  73. Ha,Jong Woo; Kim,Gwang; Park,JuHyun, Stacked integrated circuit package-in-package system.
  74. Ha,Jong Woo; Kim,Gwang; Park,JuHyun, Stacked integrated circuit package-in-package system.
  75. Yim,Choong Bin; Song,Sungmin; Lee,SeongMin; Lim,Jaehyun; Yang,Joungin; Park,DongSam, Stacked integrated circuit package-in-package system with recessed spacer.
  76. Kwon, Hyeog Chan; Karnezos, Marcos, Stacked semiconductor package having adhesive/spacer structure and insulation.
  77. Sustek, Laurent; Di Vito, Stephane, Surface mounting chip carrier module.

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로