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[미국특허] Method and device for mounting electronic component on circuit board 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0331763 (1997-12-26)
우선권정보 JP-8-350738(1996-12-27)
국제출원번호 PCT/JP97/004873 (1997-12-26)
§371/§102 date 19990625 (19990625)
국제공개번호 WO98/030073 (1998-07-09)
발명자 / 주소
  • Nishida,Kazuto
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd.
대리인 / 주소
    Wenderoth, Lind &
인용정보 피인용 횟수 : 29  인용 특허 : 37

초록

When mounting an IC chip on a circuit board, bumps are formed on electrodes of the IC chip, and the bumps and the electrodes of the circuit board are aligned in position with each other with interposition of an insulative thermosetting resin having no conductive particle between the electrodes of th

대표청구항

What is claimed is: 1. A method of mounting an electronic component, said method comprising: aligning in position bumps formed by wire-bonding on electrodes of said electronic component with electrodes of a circuit board, with interposition between said electronic component and said circuit board o

이 특허에 인용된 특허 (37) 인용/피인용 타임라인 분석

  1. Tsukagoshi Isao (Shimodate JPX) Yamaguchi Yutaka (Yuki JPX) Nakajima Atsuo (Ibaraki JPX) Mikami Yoshikatsu (Shimodate JPX) Muto Kuniteru (Shimodate JPX) Ikezoe Yoshiyuki (Yuki JPX), Anisotropic-electroconductive adhesive composition, method for connecting circuits using the same, and connected circuit.
  2. Tsukagoshi Isao (Shimodate JPX) Yamaguchi Yutaka (Yuuki JPX) Nakayama Tadamitsu (Yokohama JPX), Anisotropic-electroconductive adhesive film.
  3. Tago Masamoto (Tokyo JPX) Tanaka Kei (Tokyo JPX), Apparatus for forming a double-bump structure used for flip-chip mounting.
  4. Tomura Yoshihiro (Hirakata JPX) Bessho Yoshihiro (Higashiosaka JPX), Capillary for a wire bonding apparatus and a method for forming an electric connection bump using the capillary.
  5. Hori Takeshi (Kanagawa JPX), Chip device bonding machine.
  6. Tang Pao-Yun,TWX ; Chang Shyh-Ming,TWX ; Lee Yu-Chi,TWX ; Fang Su-Yu,TWX, Composite bump tape automated bonding method and bonded structure.
  7. Tsukagoshi Isao (Shimodate) Yamaguchi Yutaka (Yuki) Nakajima Atsuo (Ibaraki) Goto Yasushi (Shimodate JPX), Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips.
  8. Tagusa Yasunobu (Kitakatsuragi JPX) Matsubara Hiroshi (Tenri JPX) Nukii Takashi (Nara JPX), Connection construction and method of manufacturing the same.
  9. Matsumoto Seiji (Omiya JPX) Shiino Makoto (Omiya JPX), Electronic endoscope with a mask bump bonded to an image pick-up device.
  10. Eifuku Hideki,JPX ; Sakai Tadahiko,JPX, Electronic parts mounting method.
  11. Watanabe Tsutomu (Yokohama JA) Nakayama Takahiro (Yokohama JA) Yamaoka Sigenori (Yokohama JA), Flexible metal-clad laminates and method for manufacturing the same.
  12. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Flip chip interconnections on electronic modules.
  13. Ellerson James Vernon ; Funari Joseph ; Varcoe Jack Arthur, Interconnection of a carrier substrate and a semiconductor device.
  14. Pinnavaia Giuseppe R. (Rieti ITX), Method for assembling components upon printed circuit boards.
  15. Grupen-Shemansky Melissa E. ; Lin Jong-Kai ; Tessier Theodore G., Method for coupling substrates and structure.
  16. Viza Daniel Joseph ; Miller Dennis Brian ; Beckenbaugh William M. ; Monroe Conrad S.,DEX ; Hansen Kent W., Method for forming a microelectronic assembly.
  17. Bessho Yoshihiro (Higashiosaka JPX) Tomura Yoshihiro (Hirakata JPX), Method for mounting a semiconductor device on a circuit board.
  18. Klein Dean A., Method for mounting packaged integrated circuit devices to printed circuit boards.
  19. Rai Akiteru (Nara JPX), Method for mounting semiconductor chip on circuit board.
  20. George Reed A. (Lake Worth FL) Mangold Richard L. (Boynton Beach FL) Brooks Richard K. (Boynton Beach FL), Method for underencapsulating components on circuit supporting substrates.
  21. Matsuhira Tsutomu,JPX, Method of coating a conductive substance on a transparent electrode formed on a substrate and method of mounting a semic.
  22. Matsui Koji (Tokyo JPX), Method of connecting an integrated circuit chip to a substrate.
  23. Tsuda Toshio (Habikino JPX) Horio Yasuhiko (Osaka JPX) Bessho Yoshihiro (Kadoma JPX) Ishida Toru (Hirakata JPX), Method of forming an electrical contact bump.
  24. Kurogi Garrett Isao (Lakewood CA) Swass Matthew J. (El Segundo CA), Method of hermetically self-sealing a flip chip.
  25. Gamota Daniel Roman ; Wille Steven Lewis ; Scheifers Steven Michael ; Hertsberg Michael, Method of holding a component using an anhydride fluxing agent.
  26. Murakami Tomoo,JPX, Method of mounting a semiconductor device to a substrate and a mounted structure.
  27. Variot Patrick ; Chia Chok J. ; Trabucco Robert T., Method of planarizing an array of plastically deformable contacts on an integrated circuit package to compensate for sur.
  28. Kira Hidehiko,JPX ; Kobae Kenji,JPX ; Kainuma Norio,JPX ; Ishikawa Naoki,JPX ; Emoto Satoshi,JPX, Method of producing a multichip package module in which rough-pitch and fine-pitch chips are mounted on a board.
  29. Tsukagoshi Isao,JPX ; Yamaguchi Yutaka,JPX ; Nakajima Atsuo,JPX ; Goto Yasushi,JPX, Process for connecting circuits and adhesive film used therefor.
  30. Sozansky Wayne Anthony ; Gibson Michael D. ; Mack Susan Acheson ; Meehan Michael Patrick ; Peugh Darrel Eugene ; Rosson James M. ; Sellers Robin L. ; Witty Michael Ray, Process for producing flip chip circuit board assembly exhibiting enhanced reliability.
  31. Matsubara Kiyoshi (Kodaira JPX) Yamaura Tadashi (Kokubunji JPX) Kihara Toshimasa (Tachikawa JPX) Kawashimo Norishige (Tokorozawa JPX), Semiconductor device and process for producing the same.
  32. Mori Miki (Kawasaki JPX) Saito Masayuki (Yokohama JPX), Semiconductor device utilizing a face-down bonding and a method for manufacturing the same.
  33. Soga Tasao (Hitachi JPX) Goda Marahiro (Hitachi JPX) Nakano Fumio (Hitachi JPX) Kushima Tadao (Ibaraki JPX) Ushifusa Nobuyuki (Hitachi JPX) Kobayashi Fumiyuki (Sagamihara JPX) Sawahata Mamoru (Hitach, Semiconductor resin package structure.
  34. Bross Arthur (Poughkeepsie NY) Hedrick James J. (Oakland CA) Johnson Robert D. (Morgan Hill CA) Lussow Robert O. (Hopewell Junction NY) Lyerla ; Jr. James R. (San Jose CA) Myers Donald E. (Poughkeeps, Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures.
  35. Legg Stephen P. (Southampton TX GB2) Schrottke Gustav (Austin TX), Soldering method.
  36. Belke ; Jr. Robert Edward ; Hayden Brian John ; Pham Cuong Van ; Nuno Rosa Lynda ; Todd Michael George, Solderless flip-chip assembly and method and material for same.
  37. Shibuya Tsutomu,JPX ; Katayama Kaoru,JPX ; Shirai Mitugu,JPX ; Kazui Shinichi,JPX ; Sasaki Hideaki,JPX ; Iwata Yasuhiro,JPX, Surface reformation method of high polymer material.

이 특허를 인용한 특허 (29) 인용/피인용 타임라인 분석

  1. Takano, Daijiro; Fujita, Hikaru, Anisotropic conductive adhesive, electrode connection structure and method using the adhesive.
  2. Bower, Christopher; Meitl, Matthew; Gomez, David; Bonafede, Salvatore; Kneeburg, David, Apparatus and methods for micro-transfer-printing.
  3. Miyazaki, Hiroki, Chip component mounting structure, chip component mounting method and liquid crystal display device.
  4. Nishikawa, Hidenobu; Komyoji, Daido, Circuit board and process for producing the same.
  5. Nishikawa, Hidenobu; Komyoji, Daido, Circuit board and process for producing the same.
  6. Moriyama, Hironobu, Circuit connecting material and semiconductor device manufacturing method using same.
  7. Haji, Hiroshi; Ozono, Mitsuru; Kasai, Teruaki; Nonomura, Masaru, Component bonding method, component laminating method and bonded component structure.
  8. Chen, Kuan Hsin; Lai, Keng Ming; Hsiao, Chih Hung; Wang, Min Cheng, Electronic bonding structure with separately distributed anisotropic conductive film units and liquid crystal panel having same.
  9. Nishida, Kazuto; Nishikawa, Hidenobu; Wada, Yoshinori; Otani, Hiroyuki, Electronic component mounting method and apparatus.
  10. Nishida, Kazuto; Nishikawa, Hidenobu; Wada, Yoshinori; Otani, Hiroyuki, Electronic component unit.
  11. Kawaguchi, Katsuo; Futamura, Hirofumi, Flex-rigid wiring board.
  12. Mikado, Yukinobu; Sagisaka, Katsumi; Kawaguchi, Katsuo; Muraki, Tetsuya, Flex-rigid wiring board and manufacturing method thereof.
  13. Su, Chun-Wei; Leu, Chyi-Ming; Kuo, Yu-Ju; Lin, Hong-Ching; Lu, Chun-An; Chen, Chiung-Hsiung, Flexible substrate embedded with wires and method for fabricating the same.
  14. Xu, Dingying; Eitan, Amram, In-situ formation of conductive filling material in through-silicon via.
  15. Kimura,Yuji; Maeda,Takenobu; Kabe,Toru, Method for manufacturing an electronic circuit device and electronic circuit device.
  16. Healy, Christopher James, Method for manufacturing tight pitch, flip chip integrated circuit packages.
  17. Farroni,Jean Paul, Method of integrated circuit assembly.
  18. Hougham, Gareth G.; Beaman, Brian S.; Corbin, John S.; Coteus, Paul; Hall, Shawn A.; Hinge, Kathleen C.; Lewis, Theron L.; Libsch, Frank R.; Mikhail, Amanda E. E., Method of making a land-grid-array (LGA) interposer.
  19. Tomoda, Katsuhiro, Method of mounting devices in substrate and device-mounting substrate structure thereof.
  20. Yamamoto,Tsuyoshi; Suehiro,Mitsuo; Yamada,Hiroshi, Method of mounting electronic component on substrate without generation of voids in bonding material.
  21. Sammakia, Bahgat; Jones, Jr., Wayne E.; Subbarayan, Ganesh, Nano-structure enhancements for anisotropic conductive material and thermal interposers.
  22. Vittu, Julien, Semiconductor package fabrication process and semiconductor package.
  23. Sylvestre, Julien, Thermocompression for semiconductor chip assembly.
  24. Sylvestre, Julien, Thermocompression for semiconductor chip assembly.
  25. Sylvestre, Julien, Thermocompression for semiconductor chip assembly.
  26. Sylvestre, Julien, Thermocompression for semiconductor chip assembly.
  27. Workman,Derek B.; Chaundhuri,Arun K.; Berg,Eric M, Underfill method.
  28. Ano,Kazuaki, Wire bonding for thin semiconductor package.
  29. Nakahama, Hiroki, Wiring board and semiconductor device using the wiring board.

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