초록 ▼

Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration

Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

대표청구항 ▼

What is claimed is: 1. A method for iteratively decoding a received signal, the method comprising: iteratively decoding the received signal; creating a signature from values of an Nth decoding iteration; comparing the signature of the Nth iteration to a signature of an (N-1)th iteration; and sto

What is claimed is: 1. A method for iteratively decoding a received signal, the method comprising: iteratively decoding the received signal; creating a signature from values of an Nth decoding iteration; comparing the signature of the Nth iteration to a signature of an (N-1)th iteration; and stopping the process of iterative decoding if the signature of the (N-1)th iteration is equal to the signature of the Nth iteration. 2. The method of claim 1 further comprising outputting a decoded data signal related to the received signal. 3. The method of claim 1 wherein the iteratively decoding comprises computing an estimate of the received signal. 4. The method of claim 1 wherein the iteratively decoding utilizes parallel turbo codes. 5. The method of claim 1 wherein the iteratively decoding utilizes serial turbo codes. 6. The method of claim 1 wherein the iteratively decoding utilizes one or more of the group consisting of product codes, low density parity check codes (LDPC), Reed Solomon codes, graph codes, and belief propagation codes. 7. The method of claim 1 wherein the creating of the signature comprises: receiving extrinsic values from the Nth iteration; converting the extrinsic values into hard values; and accumulating the hard values in a signature circuit to form a signature. 8. The method of claim 7 wherein the accumulating the hard values comprises: receiving the hard values in a combinational circuit; receiving the output of a buffer in the combinational circuit; forming a combinational value from a hard value and the output of the buffer; providing the combinational value to the input of the buffer; and reading the state of the buffer to provide a signature value. 9. A method for iteratively decoding a received signal, the method comprising: iteratively decoding the received signal; creating a signature from values of an Nth decoding iteration; comparing the signature of the Nth iteration to a signature of an (N-2)th iteration; and stopping the process of iterative decoding if the signature of the (N-2)th iteration is equal to the signature of the Nth iteration. 10. The method of claim 9 further comprising outputting a decoded data signal related to the received corrupted data signal. 11. The method of claim 9 wherein the iteratively decoding comprises computing an estimate of the received signal. 12. The method of claim 9 wherein the iteratively decoding utilizes parallel turbo codes. 13. The method of claim 9 wherein the iteratively decoding utilizes serial turbo codes. 14. The method of claim 9 wherein the iteratively decoding utilizes one or more of the group consisting of product codes, low density parity check codes (LDPC), Reed Solomon codes, graph codes, and belief propagation codes. 15. The method of claim 9 wherein the creating of the signature comprises: receiving extrinsic values from the Nth iteration; converting the extrinsic values into hard values; and accumulating the hard values in a signature circuit to form a signature. 16. The method of claim 15 wherein the accumulating the hard values in a signature circuit comprises: receiving the hard values in a combinational circuit; receiving the output of a buffer into the combinational circuit; forming a combinational value from a hard value and the output of the buffer; providing the combinational value to the input of the buffer; and reading the state of the buffer to provide a signature value. 17. An iterative decoder comprising: means for iteratively decoding a received signal; means for generating a signature from values of an Nth decoding iteration; means for comparing the signature of the Nth iteration to a signature of an (N-1)th iteration; and means for stopping the process of iterative decoding if the signature of the (N-1)th iteration is equal to the signature of the Nth iteration. 18. The iterative decoder of claim 17 further comprising means for outputting a decoded data signal related to the received corrupted data signal. 19. The iterative decoder of claim 17 wherein the means for iteratively decoding comprises means for computing an estimate of the received signal. 20. The iterative decoder of claim 17 wherein the means for iteratively decoding utilizes parallel turbo codes. 21. The iterative decoder of claim 17 wherein the means for iteratively decoding utilizes serial turbo codes. 22. The iterative decoder of claim 17 wherein the means for iteratively decoding utilizes one or more of the group consisting of product codes, low density parity check codes (LDPC), Reed Solomon codes, graph codes, and belief propagation codes. 23. The iterative decoder of claim 17 wherein the means for generating a signature comprises: means for receiving extrinsic values from the Nth iteration; a converter for converting the extrinsic values into hard values; and a signature circuit for accumulating the hard values to form a signature. 24. The iterative decoder of claim 23 wherein the signature circuit comprises: a combinational circuit for receiving the hard values; means for receiving the output of a buffer in the combinational circuit; means for forming a combinational value from a hard value and the output of the buffer; means for providing the combinational value to the input of the buffer; and means for reading the state of the buffer to provide a signature value.