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Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0997987 (2001-11-30)
발명자 / 주소
  • Master,Paul L.
  • Smith,Stephen J.
  • Watson,John
출원인 / 주소
  • Quick Silver Technology, Inc.
인용정보 피인용 횟수 : 64  인용 특허 : 26

초록

The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit to provide an operating mode. The preferred exe

대표청구항

What is claimed is: 1. A system for configuring and operating an adaptive circuit, the system comprising: a first routable and executable information module, the module having first configuration information and second configuration information, the module further having first operand data and seco

이 특허에 인용된 특허 (26)

  1. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  2. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.
  3. Holtzman, Jack M.; Bao, Gang, Forward-link scheduling in a wireless communication system during soft and softer handoff.
  4. Law Edwin S. ; Buch Kiran B. ; Baxter Glenn A. ; Pang Raymond C., Hardwire logic device emulating an FPGA.
  5. Stephen L. Wasson, Heterogeneous programmable gate array.
  6. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  7. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
  8. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  9. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  10. Master Paul L. ; Hatley William T. ; Scheuermann II Walter J. ; Goodman Margaret J., Method and apparatus for adaptable digital protocol processing.
  11. Cummings Mark R., Method and apparatus for communicating information.
  12. Walton, Jay R.; Wallace, Mark; Ketchum, John W.; Howard, Steven J., Method and apparatus for processing data in a multiple-input multiple-output (MIMO) communication system utilizing channel state information.
  13. Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
  14. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  15. Harrison David A. ; Silver Joshua M. ; Soe Soren T., Method for programming complex PLD having more than one function block type.
  16. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  17. Katsutoshi Ito JP, Radio communication apparatus employing a rake receiver.
  18. Ebeling William Henry Carl ; Cronquist Darren Charles ; Franklin Paul David, Reconfigurable computing architecture for providing pipelined data paths.
  19. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
  20. Trimberger Stephen M., Reprogrammable instruction set accelerator.
  21. Kelleher Brian M. ; Dewey Thomas E., Scalable graphics processor architecture.
  22. Kopp Randall L. (Irvine CA) Johnson S. Val (Anaheim CA), Single-chip self-configurable parallel processor.
  23. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
  24. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
  25. Agrawal Prathima ; Cravatts Mark Robert ; Trotter John Andrew ; Srivastava Mani Bhushan, Wireless adapter architecture for mobile computing.
  26. Athanas Peter ; Bittner ; Jr. Ray A., Worm-hole run-time reconfigurable processor field programmable gate array (FPGA).

이 특허를 인용한 특허 (64)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Fisher, Louis Cameron; Hellriegel, Stephen V. R.; Ahmadnia, Mohammad S., Adaptive memory system for enhancing the performance of an external computing device.
  10. Fisher, Louis Cameron; Hellriegel, Stephen V. R.; Ahmadnia, Mohammad S., Adaptive memory system for enhancing the performance of an external computing device.
  11. Fisher, Louis Cameron; Hellriegel, Stephen V. R.; Ahmadnia, Mohammad S., Adaptive memory system for enhancing the performance of an external computing device.
  12. Fisher, Louis Cameron; Hellriegel, Stephen V. R.; Ahmadnia, Mohammad S., Adaptive memory system for enhancing the performance of an external computing device.
  13. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  14. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  15. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  16. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  17. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  21. Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  22. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  23. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  24. Taylor,Richard Michael, Automatic configuration of a microprocessor influenced by an input program.
  25. Collins,Anthony J.; Schultz,David P.; Jacobson,Neil G.; McGettigan,Edward S.; Fross,Bradley K., Boundary-scan circuit used for analog and digital testing of an integrated circuit.
  26. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  27. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  29. Harada, Yoshihiro; Takao, Shinji; Kitamura, Kiyoshi; Takata, Isao, Data processing apparatus and method.
  30. Malina, James N.; Sujanto, Totok Sulistiomono; Dong, Li, Data storage device and method providing non-volatile memory buffer for real-time primary non-volatile memory protection.
  31. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  32. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  33. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  34. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  35. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  39. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  40. Salama, Yassir; Salama, Assem; Fitzgerald, Dennis, High speed and efficient matrix multiplication hardware module.
  41. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  42. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  43. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  44. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  45. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  46. Rathi, Manish M.; Jain, Vipin K.; Merchant, Shehzad T.; Lin, Victor C., Method and system for detecting and preventing access intrusion in a network.
  47. Rathi, Manish M.; Jain, Vipin K.; Merchant, Shehzad T.; Lin, Victor C., Method and system for detecting and preventing access intrusion in a network.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  51. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  53. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  54. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  55. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  56. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  57. Kurosawa, Takahiro, Processor delivering content information recovered upon sequence of processes performed by data path reconfigured based on received configuration information containing use frequency.
  58. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  59. Houshaku, Masahiro, Reconfigurable signal processor.
  60. Giaretta, Gerardo; Guardini, Ivano, Routing method, system, corresponding network and computer program product.
  61. Master,Paul L.; Watson,John, Storage and delivery of device features.
  62. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  63. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  64. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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