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Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volu

Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

대표청구항 ▼

We claim: 1. A method of forming a strained silicon on an insulator substrate comprising providing a silicon substrate; depositing a SiGe layer directly on the silicon substrate whereby a silicon/SiGe interface is formed between the silicon substrate and the deposited SiGe layer; implanting relax

We claim: 1. A method of forming a strained silicon on an insulator substrate comprising providing a silicon substrate; depositing a SiGe layer directly on the silicon substrate whereby a silicon/SiGe interface is formed between the silicon substrate and the deposited SiGe layer; implanting relaxing ions through the SiGe layer into the silicon substrate to a depth of between about 10 nm to 30 nm; annealing to convert the SiGe layer to a relaxed SiGe layer; depositing an epitaxial silicon layer overlying the relaxed SiGe layer; and transferring the epitaxial silicon/SiGe multilayer to an insulator substrate. 2. A method as in claim 1 wherein the SiGe layer thickness is in the range of 250 to 350 nm. 3. A method as in claim 1 wherein the relaxing ion implantation is performed by plasma immersion ion implantation. 4. A method as in claim 1 wherein the implanted relaxing ions comprise molecular hydrogen ions (H230). 5. claim 1 wherein the implanted relaxing ions comprise hydrogen atom ions (H+), helium, boron, silicon, argon or any combinations thereof. 6. A method as in claim 1 wherein the dosage of the implanted relaxing ions is in the range of 2횞1014 to 2횞1016 cm-2 and the energy of the implanted relaxing ions is in the range of 10 to 120 keV. 7. A method as in claim 1 further comprising an additional implantation of the SiGe layer with a species selected from boron, helium and silicon before or after the relaxed relaxing ion implantation with a dosage range of 1012 to 1015 cm-2. 8. A method as in claim 1 wherein the annealing comprises an annealing in the temperature range of 350 to 1000째 C. for a period of time ranging from 0.1 to 4 hours. 9. A method as in claim 1 wherein the annealing comprises a two step annealing, wherein a first anneal step includes annealing at a temperature of between about 350째 C.-400째 C., for between about 10 minutes-4 hours, and a second anneal step includes annealing at a temperature of between about 450째 C.-1000째 C., for between about 1 minute-60 minutes. 10. A method as in claim 1 wherein the thickness of the epitaxial silicon layer is in the range of 10 to 100 nm. 11. A method as in claim 1 further comprising a SiGe polishing step and a post polishing cleaning step before the deposition of the epitaxial silicon layer. 12. A method as in claim 1 wherein transferring the epitaxial silicon/SiGe multilayer to an insulator substrate comprises implanting splitting ions into the epitaxial silicon/SiGe multilayer to generate a defect zone under the epitaxial silicon/SiGe interface; bonding the epitaxial silicon layer surface of silicon substrate to an insulator layer on a second substrate to form a bonded composite substrate; and thermally annealing the composite substrate to split the epitaxial silicon/SiGe multilayer along the defect zone. 13. A method of forming a strained silicon on an insulator substrate comprising providing a silicon substrate; depositing a SiGe layer directly on the silicon substrate whereby a silicon/SiGe interface is formed between the silicon substrate and the deposited SiGe layer; implanting relaxing ions through the SiGe layer into the silicon substrate; annealing to convert the SiGe layer to a relaxed SiGe layer; polishing and cleaning the SiGe layer to improve the SiGe surface; depositing an epitaxial silicon layer overlying the relaxed SiGe layer; implanting splitting ions into the epitaxial silicon/SiGe multilayer to generate a defect zone below the silicon/SiGe interface wherein the projected range of the implanted ions is about 100 to 500 nm into the silicon substrate; bonding the epitaxial silicon layer surface of silicon substrate to an insulator layer on a second substrate to form a bonded composite substrate; low temperature annealing the composite substrate to split the epitaxial silicon/SiGe multilayer along the defect zone at temperature below 400째 C.; dry etching to remove part of the silicon substrate and part of the SiGe layer; high temperature annealing the composite substrate to improve the bonding at temperature above 400째 C.; and etching the remaining SiGe layer by a polishing process or by selective wet etch process or by a combination of polishing and selective wet etch process. 14. A method as in claim 13 wherein the SiGe layer thickness is in the range of 250 to 350 nm. 15. A method as in claim 13 wherein either the relaxing ion implantation or the splitting ion implantation is performed by plasma immersion ion implantation. 16. A method as in claim 13 wherein either the implanted relaxing ions or the implanted splitting ions comprise molecular hydrogen ions (H2+). 17. A method as in claim 13 wherein either the implanted relaxing ions or the implanted splitting ions comprise hydrogen atom ions (H+), helium, boron, silicon, argon or any combinations thereof. 18. A method as in claim 13 wherein the projected range of the implanted relaxing ions is about 10 to 30 nm into the silicon substrate. 19. A method as in claim 13 wherein the dosage of the implanted relaxing ions is in the range of 2횞1014 to 2횞1016 cm-2. 20. A method as in claim 13 wherein the energy of the implanted relaxing ions is in the range of 10 to 120 keV. 21. A method as in claim 13 further comprising an additional implantation of the SiGe layer with a species selected from boron, helium and silicon before or after the relaxing ion implantation and with the dosage range of 1012 to 1015 cm-2. 22. A method as in claim 13 wherein the annealing to convert comprises an annealing in the temperature range of 450 to 1000째 C. for a period of time ranging from 0. 1 to 4 hours. 23. A method as in claim 13 wherein the annealing to convert comprising a two step annealing, wherein a first anneal step includes annealing at a temperature of between about 350째 C.-400째 C., for between about 10 minutes-4 hours, and a second anneal step includes annealing at a temperature of between about 450째 C.-1000째 C., for between about 1 minute-60 minutes. 24. A method as in claim 13 wherein the thickness of the epitaxial silicon layer is in the range of 10 to 300 nm. 25. A method as in claim 13 wherein the dosage of the implanted split splitting ions is in the range of 1016 to 2횞1017 cm-2. 26. A method as in claim 13 wherein the energy of the implanted splitting ions is less than 300 keV. 27. A method as in claim 13 further comprising an additional implantation of the SiGe layer with a species selected from boron, helium and silicon before or after the splitting ion implantation and with the dosage range of 1012 to 1015 cm-2.