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In a power source for an electric arc welder including an inverter having two primary circuits connected in a series circuit across the DC bus of an input rectifier where each primary circuit comprises a capacitor parallel with a primary winding section and a switch to apply the voltage of the capac

In a power source for an electric arc welder including an inverter having two primary circuits connected in a series circuit across the DC bus of an input rectifier where each primary circuit comprises a capacitor parallel with a primary winding section and a switch to apply the voltage of the capacitor across the primary winding section, so that the primary circuits alternately create a voltage pulse in the primary winding sections to induce voltage pulses in a secondary circuit having a secondary winding coupled to said primary windings and connected by an output circuit to an output welding circuit. There is provided one improvement. The improvement is a soft ferrite saturable reactor in at least one of the series circuit or the output circuit to delay the voltage pulse in the primary winding sections.

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Having thus described the invention, the following is claimed: 1. In a power source for an electric arc welder including an inverter having two primary circuits connected in a series circuit across the DC bus of an input rectifier, each of said primary circuits comprising a capacitor in parallel wi

Having thus described the invention, the following is claimed: 1. In a power source for an electric arc welder including an inverter having two primary circuits connected in a series circuit across the DC bus of an input rectifier, each of said primary circuits comprising a capacitor in parallel with a primary winding section and a switch to apply the voltage of said capacitor across said primary winding section, whereby said primary circuits alternately create a voltage pulse in said primary winding sections to induce voltage pulses in a secondary circuit having a secondary winding coupled to said primary windings and connected by an output circuit to an output welding circuit, the improvement comprising: a soft ferrite saturable reactor in at least one of said series circuit or said output circuit to delay said voltage pulse in said primary winding sections and wherein said saturable reactor is passive and has a fixed saturation flux density. 2. The improvement as defined in claim 1 wherein said saturable reactor is in said output circuit. 3. The improvement as defined in claim 2 wherein the saturable reactor has a saturation flux density less than 0.50 Tesla. 4. The improvement as defined in claim 3 wherein said saturable reactor has a ratio of surface area to volume greater than 3.5 cm2/cm3. 5. The improvement as defined in claim 4 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 6. The improvement as defined in claim 5 wherein said ring has a length greater than its outside diameter. 7. The improvement as defined in claim 5 wherein the cross-section of said ring is a rectangle having a width greater than its height. 8. The improvement as defined in claim 3 wherein said saturable reactor is pipe-shaped and has a ratio of surface area to volume greater than 3.5 cm2/cm3 and wherein said saturable reactor includes an outer heat sink tube that is formed from a highly conductive material and has a cylindrical base with outwardly expanding fins and an expandable assembly gap. 9. The improvement as defined in claim 8 wherein said delay is at least 0.5 microseconds but not more than 3 microseconds. 10. The improvement as defined in claim 3 wherein said saturable reactor is pancake-shaped with heat sink disks to dissipate heat and has a ratio of surface area to volume greater than 3.5 cm2/cm3 and wherein said disks have holes at least as large as the internal diameter of said saturable reactor. 11. The improvement as defined in claim 10 wherein said delay is at least 0.5 microseconds but not more than 3 microseconds. 12. The improvement as defined in claim 3 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 13. The improvement a defined in claim 12 wherein said ring has a length greater than its outside diameter. 14. The improvement defined in claim 12 wherein the cross-section of said ring is a rectangle having a width greater than its height. 15. The improvement as defined in claim 2 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 16. The improvement as defined in claim 15 wherein said ring has a length greater than its outside diameter. 17. The improvement as defined in claim 15 wherein the cross-section of said ring is a rectangle having a width greater than its height. 18. The improvement as defined in claim 2 wherein said delay is at least 0.5 microseconds. 19. The improvement as defined in claim 1 wherein the saturable reactor has a saturation flux density less than 0.50 Tesla. 20. The improvement as defined in claim 19 wherein said saturable reactor has a ratio of surface area to volume greater than 3.5 cm2/cm3. 21. The improvement as defined in claim 20 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 22. The improvement as defined in claim 21 wherein said ring has a length greater than its outside diameter. 23. The improvement as defined in claim 21 wherein the cross-section of said ring is a rectangle having a width greater than its height. 24. The improvement as defined in claim 19 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 25. The improvement defined in claim 24 wherein said ring has a length greater than its outside diameter. 26. The improvement as defined in claim 24 wherein the cross-section of said ring is a rectangle having a width greater than its height. 27. The improvement as defined in claim 19 wherein said delay is at least 0.5 microseconds. 28. The improvement as defined in claim 1 wherein said output circuit is a rectifier with two input leads and said saturable reactor is a ring surrounding both of said leads. 29. The improvement as defined in claim 28 wherein said ring has a length greater than its outside diameter. 30. The improvement as defined in claim 28 wherein the cross-section of said ring is a rectangle having a width greater than its height. 31. The improvement as defined in claim 28 wherein said delay is at least 0.5 microseconds. 32. The improvement as defined in claim 1 wherein said delay is at least 0.5 microseconds. 33. In a pulsed transformer of an inverter driven welder, which transformer has a pulsed primary winding network and a secondary winding network, the improvement comprising: a soft ferrite, passive saturable reactor in series with said transformer, said saturable reactor includes a heat sink tube around said a ring and has a fixed saturation flux density and wherein said saturable reactor delays pulses in said primary winding network by at least 0.5 microseconds and said heat sink tube is formed from a highly conductive material and has a cylindrical base with outwardly expanding fins and an expandable assembly gap. 34. In a pulsed transformer of an inverter driven welder, which transformer has a pulsed primary winding network and a secondary winding network, the improvement comprising: a passive saturable reactor in series with said transformer, said saturable reactor is a soft ferrite ring with a cross-section as a rectangle having a width greater than its height and has a fixed saturation flux density and wherein said saturable reactor delays pulses in said primary winding network by at least 0.5 microseconds. 35. In a pulsed transformer of an inverter driven welder, which transformer has a pulsed primary winding network and a secondary winding network, the improvement comprising: a soft ferrite saturable reactor in series with said transformer, said saturable reactor is passive and has a fixed saturation flux of less than 0.40 tesla and wherein said saturable reactor delays pulses in said primary winding network by at least 0.5 microseconds.