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A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function req

A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

대표청구항 ▼

What is claimed is: 1. For use with a fast pattern processor having an internal function bus and an external function bus, a function interface system, comprising: a controller arbitration subsystem configured to arbitrate access to a block buffer containing processing blocks associated with a prot

What is claimed is: 1. For use with a fast pattern processor having an internal function bus and an external function bus, a function interface system, comprising: a controller arbitration subsystem configured to arbitrate access to a block buffer containing processing blocks associated with a protocol data unit (PDU) and process an issued function request received from at least one of said internal function bus and said external function bus; and a dispatch subsystem configured to retrieve said issued function request from a queue associated with said controller arbitration subsystem and dispatch said issued function request to at least one associated co-processor via said controller arbitration subsystem. 2. The function interface system as recited in claim 1 wherein said queue is a function queue subsystem configured to manage a plurality of function request queues and queue said issued function request. 3. The function interface system as recited in claim 1 further comprises an external function bus subsystem configured to process said issued function request associated with a co-processor via said external function bus. 4. The function interface system as recited in claim 3 wherein said dispatch subsystem is further configured to dispatch said issued function request to said external function bus subsystem. 5. The function interface system as recited in claim 1 further comprises an argument signature register having a plurality of memory locations that contain an argument, associated with a context, to be passed between a pattern processing engine and said at least one associated co-processor, said controller arbitration subsystem further configured to arbitrate access to said argument signature register. 6. The function interface system as recited in claim 1 wherein said at least one associated co-processor is selected from the group consisting of: a queue engine, an arithmetic logic unit, a checksum engine, and a system interface processor. 7. The function interface system as recited in claim 1 further comprises a scheduler subsystem configured to manage a context associated with said processing blocks and schedule processing in a pattern processing engine based upon a context. 8. The function interface system as recited in claim 7 wherein said pattern processing engine comprises a first and second flow engine configured to process one of said processing blocks based upon said context. 9. The function interface system as recited in claim 8 wherein said first flow engine processes even number contexts and said second flow engine processes odd number contexts. 10. For use with a fast pattern processor having an internal function bus and an external function bus, a method of processing issued function requests, comprising: processing an issued function request received from at least one of said internal function bus and said external function bus, said processing including arbitrating access to a block buffer containing processing blocks associated with a protocol data unit (PDU); and dispatching said issued function request to at least one associated co-processor via a controller arbitration subsystem. 11. The method as recited in claim 10 further comprising managing a plurality of function request queues and queuing said issued function request, said dispatching further includes retrieving said issued function request from said function request queues. 12. The method as recited in claim 10 further comprising processing said issued function request associated with a co-processor via said external function bus. 13. The method as recited in claim 12 wherein said dispatching further includes dispatching said issued function request to said external function bus. 14. The method as recited in claim 10 further comprising an argument signature register having a plurality of memory locations that contain an argument, associated with a context, to be passed between a pattern processing engine and said at least one associated co-processor, said processing further includes arbitrating access to said argument signature register. 15. The method as recited in claim 10 wherein said at least one associated co-processor is selected from the group consisting of: a queue engine, an arithmetic logic unit, a checksum engine, and a system interface processor. 16. The method as recited in claim 10 further comprises managing a context associated with said processing blocks and scheduling processing in a pattern processing engine based upon a context. 17. The method as recited in claim 16 wherein said pattern processing engine comprises a first and second flow engine configured to process one of said processing blocks based upon said context. 18. The method as recited in claim 17 wherein said first flow engine processes even number contexts and said second flow engine processes odd number contexts. 19. For use with a fast pattern processor having an internal function bus and an external function bus, a function interface system, comprising: a controller arbitration subsystem configured to process an issued function request received from at least one of said internal function bus and said external function bus; a dispatch subsystem configured to retrieve said issued function request from a queue associated with said controller arbitration subsystem and dispatch said issued function request to at least one associated co-processor via said controller arbitration subsystem; and an argument signature register having a plurality of memory locations that contain an argument, associated with a context, to be passed between a pattern processing engine and said at least one associated co-processor, said controller arbitration subsystem further configured to arbitrate access to said argument signature register. 20. The function interface system as recited in claim 19 wherein said queue is a function queue subsystem configured to manage a plurality of function request queues and queue said issued function request. 21. The function interface system as recited in claim 19 further comprises an external function bus subsystem configured to process said issued function request associated with a co-processor via said external function bus. 22. The function interface system as recited in claim 21 wherein said dispatch subsystem is further configured to dispatch said issued function request to said external function bus subsystem. 23. The function interface system as recited in claim 19 wherein said at least one associated co-processor is selected from the group consisting of: a queue engine, an arithmetic logic unit, a checksum engine, and a system interface processor. 24. The function interface system as recited in claim 19 wherein said controller arbitration subsystem arbitrates access to a block buffer containing processing blocks associated with a protocol data unit (PDU). 25. The function interface system as recited in claim 24 further comprises a scheduler subsystem configured to manage a context associated with said processing blocks and schedule processing in a pattern processing engine based upon a context. 26. The function interface system as recited in claim 25 wherein said pattern processing engine comprises a first and second flow engine configured to process one of said processing blocks based upon said context. 27. The function interface system as recited in claim 26 wherein said first flow engine processes even number contexts and said second flow engine processes odd number contexts. 28. For use with a fast pattern processor having an internal function bus and an external function bus, a function interface system, comprising: a controller arbitration subsystem configured to process an issued function request received from at least one of said internal function bus and said external function bus; a dispatch subsystem configured to retrieve said issued function request from a queue associated with said controller arbitration subsystem and dispatch said issued function request to at least one associated co-processor via said controller arbitration subsystem; and an external function bus subsystem configured to process said issued function request associated with a co-processor via said external function bus, said dispatch subsystem configured to dispatch said issued function request to said external function bus subsystem. 29. The function interface system as recited in claim 28 wherein said queue is a function queue subsystem configured to manage a plurality of function request queues and queue said issued function request. 30. The function interface system as recited in claim 28 further comprises an argument signature register having a plurality of memory locations that contain an argument, associated with a context, to be passed between a pattern processing engine and said at least one associated co-processor, said controller arbitration subsystem further configured to arbitrate access to said argument signature register. 31. The function interface system as recited in claim 28 wherein said at least one associated co-processor is selected from the group consisting of: a queue engine, an arithmetic logic unit, a checksum engine, and a system interface processor. 32. The function interface system as recited in claim 28 wherein said controller arbitration subsystem arbitrates access to a block buffer containing processing blocks associated with a protocol data unit (PDU). 33. The function interface system as recited in claim 32 further comprises a scheduler subsystem configured to manage a context associated with said processing blocks and schedule processing in a pattern processing engine based upon a context. 34. The function interface system as recited in claim 33 wherein said pattern processing engine comprises a first and second flow engine configured to process one of said processing blocks based upon said context. 35. The function interface system as recited in claim 34 wherein said first flow engine processes even number contexts and said second flow engine processes odd number contexts.