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System, method and computer program product for branching during programmable vertex processing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G09G-005/37
  • G09G-005/36
  • G06T-001/60
출원번호 US-0391930 (2003-03-19)
발명자 / 주소
  • Lindholm,John Erik
  • Moy,Simon S.
  • Glanville,Robert Steven
출원인 / 주소
  • NVIDIA Corporation
대리인 / 주소
    Zilka Kotab, PC
인용정보 피인용 횟수 : 30  인용 특허 : 41

초록

A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are assoc

대표청구항

What is claimed is: 1. A method for branching during graphics processing, comprising: performing a first operation on data; and in response to the first operation, branching to a second operation; wherein the first operation and the second operation are associated with instructions selected from a

이 특허에 인용된 특허 (41)

  1. Duluk ; Jr. Jerome F. (Mountain View CA) Kasle David B. (Mountain View CA), Bounding box and projections detection of hidden polygons in three-dimensional spatial databases.
  2. Duluk ; Jr. Jerome F. (Santa Clara County CA), Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units.
  3. Duluk ; Jr. Jerome F. (304 Emerson St. Palo Alto CA 94306), Content-addressable memory system capable of fully parallel magnitude comparisons.
  4. Sfarti Adrian ; Baker Nicholas Robert ; Laker Robert William ; Malamy Adam Craig, Controlling a real-time rendering engine using a list-based control mechanism.
  5. Duluk ; Jr. Jerome F. ; Hessel Richard E. ; Arnold Vaughn T. ; Benkual Jack ; Bratt Joseph P. ; Cuan George ; Dodgen Stephen L. ; Fang Emerson S. ; Gong Zhaoyu ; Ho Thomas Y. ; Hsu Hengwei ; Li Sidon, Deferred shading graphics pipeline processor.
  6. Duluk ; Jr. Jerome F. ; Hessel Richard E. ; Arnold Vaughn T. ; Benkual Jack ; Bratt Joseph P. ; Cuan George ; Dodgen Stephen L. ; Fang Emerson S. ; Gong Zhaoyu ; Ho Thomas Y. ; Hsu Hengwei ; Li Sidon, Deferred shading graphics pipeline processor.
  7. Ravi Shankar ; Subramania I. Sudharsanan, Division unit in a processor using a piece-wise quadratic approximation technique.
  8. Harris Kathleen A. ; Pinedo David, Dynamic selection of lighting coordinates in a computer graphics system.
  9. Kimura Koichi,JPX ; Ogura Toshihiko,JPX ; Aotsu Hiroaki,JPX ; Ikegami Mitsuru,JPX ; Kuwabara Tadashi,JPX ; Enomoto Hiromichi,JPX ; Kyoda Tadashi,JPX, Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on.
  10. McDonald Ryan O. ; Kudukoli Ramprasad ; Richardson Gregory C., Graphical code generation wizard for automatically creating graphical programs.
  11. Tucker S Paul ; Krech ; Jr. Alan S., Graphics accelerator with improved lighting processor.
  12. Saunders Bradley L. ; Johnson Brett E., Graphics application programming interface avoiding repetitive transfer of texture mapping data.
  13. Gulley David W. (Sugar Land TX) Van Aken Jerry R. (Sugar Land TX), Graphics floating point coprocessor having matrix capabilities.
  14. Chauvin Joseph W. ; Gabriel Steven A. ; Good Howard ; Griffin Kent E. ; Kenworthy Mark L. ; Powell ; III William Chambers ; Scott ; III George Easton ; Toelle Michael A. ; Torborg ; Jr. John G. ; Ver, Graphics rendering device and method for operating same.
  15. Baldwin David Robert,GBX, Graphics rendering system with reconfigurable pipeline sequence.
  16. Patrick C. McGeer ; Szu-Tsung Cheng ; Michael J. Meyer ; Patrick Scaglia, Hardware design language for the design of integrated circuits.
  17. Longhenry Brian E. ; Thome Gary W. ; Thayer John S., Line drawing using operand routing and operation selective multimedia extension unit.
  18. Duluk ; Jr. Jerome F. ; Hessel Richard E. ; Grass Joseph P. ; Rashid Abbas ; Hong Bo ; Mammen Abraham, Method and apparatus for generating texture.
  19. Pawate Basavaraj I. ; Prince Betty, Method and apparatus for improved graphics/image processing using a processor and a memory.
  20. Barkans Anthony C, Method and apparatus for providing polygon pixel sub-sample information using incremental means.
  21. Duluk ; Jr. Jerome F. (Santa Clara County CA), Method and apparatus for simultaneous parallel query graphics rendering Z-coordinate buffer.
  22. Duluk ; Jr. Jerome F., Method and apparatus for span and subspan sorting rendering system.
  23. Duluk ; Jr. Jerome F., Method and apparatus for span and subspan sorting rendering system.
  24. Duluk ; Jr. Jerome F. (Palo Alto CA), Method and apparatus for spatial simulation acceleration.
  25. Koyamada Koji (Hadano JPX), Method and apparatus for visualization of iso-valued surfaces.
  26. Snyder John M. ; Kajiya James T. ; Gabriel Steven A. ; Toelle Michael A., Method and system for improving shadowing in a graphics rendering system.
  27. Elliott Conal M. ; Knoblock Todd B. ; Schechter Greg D. ; AbiEzzi Salim S. ; Campbell Colin L. ; Yeung Chun-Fu Ricky, Method and system for modeling and presenting integrated media with a declarative modeling language for representing re.
  28. Schroeder William J. (Schenectady NY) Volpe Christopher R. (Schenectady NY), Method for graphical display of three-dimensional vector fields.
  29. Peercy Mark Stuart ; Airey John Milligan ; Cabral Brian Keith, Method, system, and computer program product for shading.
  30. Koss Louise A. ; Krech ; Jr. Alan S., Polyline and triangle strip data management techniques for enhancing performance of computer graphics system.
  31. Strunk Glenn W. ; Rojas Edmundo ; Rossin Theodore G., Post transformation clipping in a geometry accelerator.
  32. Yamazaki Shunpei,JPX ; Teramoto Satoshi,JPX, Process for fabricating semiconductor device and apparatus for fabricating semiconductor device.
  33. Krech ; Jr. Alan S. ; Rossin Theodore G. ; Rojas Edmundo ; McGrath Michael S ; Rakel Ted ; Strunk Glenn W ; Ashburn Jon L ; Tucker S Paul, ROM-based control unit in a geometry accelerator for a computer graphics system.
  34. Nelson Scott R. ; Deering Michael F., Rapid computation of local eye vectors in a fixed point lighting unit.
  35. Vainsencher Leonardo, Single chip computer having integrated MPEG and graphical processors.
  36. Fielder Dennis (Linton GBX) Derbyshire James (Willingham GBX) Gillingham Peter (Kanata CAX) Torrance Randy (Ottawa CAX) O\Connell Cormac (Kanata CAX), Single chip frame buffer and graphics accelerator.
  37. Chen Chih-Kang (Santa Clara County CA) Duluk ; Jr. Jerome F. (Santa Clara County CA), System and method for cross correlation with application to video motion vector estimator.
  38. Tarolli Gary ; Sellers Scott, System and method for efficiently determining a fog blend value in processing graphical images.
  39. Young Eric S. ; Zhao Randy X. ; Khurana Anoop ; Niu Roger ; Kuo Dong-Ying ; Kottapalli Sreenivas R., System and method for performing blending using an over sampling buffer.
  40. Hansen Craig ; Moussouris John, System and method for providing a wide operand architecture.
  41. Harris Kathleen A. ; Jensen Kimberly Wagner, System for distinguishing front facing and back facing primitives in a computer graphics system using area calculations in homogeneous coordinates.

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  2. Bakalash, Reuven; Leviathan, Yaniv, Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board.
  3. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus.
  4. Bakalash, Reuven; Remez, Offir; Fogel, Efi, Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction.
  5. Bakalash, Reuven; Leviathan, Yaniv, Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications.
  6. Bakalash, Reuven; Shoshan, Yoel; Sela, Guy, Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications.
  7. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system.
  8. Remez, Offir, Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization.
  9. Bakalash, Reuven; Leviathan, Yaniv, Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations.
  10. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Method of providing a PC-based computing system with parallel graphics processing capabilities.
  11. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus.
  12. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application.
  13. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application.
  14. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application.
  15. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation.
  16. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation.
  17. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router.
  18. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications.
  19. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application.
  20. Bakalash, Reuven; Leviathan, Yaniv, PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications.
  21. Bakalash, Reuven; Leviathan, Yaniv, Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS.
  22. Bakalash, Reuven; Remez, Offir; Fogel, Efi, Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem.
  23. Remez, Offir; Shoshan, Yoel; Sela, Guy, Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem.
  24. Brown,Patrick R.; Kilgard,Mark J.; Glanville,Robert Steven, System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipeline.
  25. Lindholm, John Erik; Kirk, David B.; Moreton, Henry P.; Moy, Simon, System, method and article of manufacture for a programmable processing model with instruction set.
  26. Lindholm, John Erik; Kirk, David B.; Moreton, Henry P.; Moy, Simon, System, method and article of manufacture for a programmable processing model with instruction set.
  27. Lindholm, John Erik; Kirk, David B.; Moreton, Henry P.; Moy, Simon, System, method and article of manufacture for a programmable processing model with instruction set.
  28. Lindholm, John Erik; Kirk, David B.; Moreton, Henry P.; Moy, Simon, System, method and article of manufacture for a programmable processing model with instruction set.
  29. Lindholm, John Erik; Moy, Simon S.; Glanville, Robert Steven, System, method and computer program product for branching during programmable vertex processing.
  30. Greene, Edward Colton; Hanrahan, Patrick Matthew, System, method and computer program product for updating a far clipping plane in association with a hierarchical depth buffer.
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