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Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/441
  • H01L-021/02
출원번호 US-0139052 (2002-05-03)
발명자 / 주소
  • Dubin,Valery M.
  • Cheng,Chin Chang
  • Hussein,Makarem
  • Nguyen,Phi L.
  • Brain,Ruth A.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 19  인용 특허 : 33

초록

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interc

대표청구항

What is claimed is: 1. A method comprising recessing an interconnect line relative to a dielectric layer in which the interconnect line is disposed by selectively removing material of the interconnect line relative to material of the dielectric layer; electrolessly depositing a conductive material

이 특허에 인용된 특허 (33)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
  2. Barth, Hans-Joachin; Kaltalioglu, Erdem, Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices.
  3. Kakizawa Masahiko,JPX ; Umekita Ken-ichi,JPX ; Hayashida Ichiro,JPX, Cleaning agent for a semi-conductor substrate.
  4. Hsiung Chiung-Sheng,TWX ; Hsieh Wen-Yi,TWX ; Lur Water,TWX, Copper damascene technology for ultra large scale integration circuits.
  5. James A. Cunningham, Diffusion barriers for copper interconnect systems.
  6. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  7. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  8. Kumasaka Osamu (Yamanashi JPX) Yamaoka Nobuki (Yamanashi JPX), Electroless plating method and apparatus.
  9. Mehta Sunil (San Jose CA), High density multi-level metallization and interconnection structure.
  10. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  11. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  12. DeLuca Michael A. (Holbrook NY) McCormack John F. (Roslyn Heights NY), Metallization of ceramics.
  13. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  14. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  15. Steven C. Avanzino ; Kai Yang ; Sergey Lopatin ; Todd P. Lukanc, Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film.
  16. Hsu Shih-Ying,TWX, Method of fabricating metal interconnect.
  17. Orita, Toshiyuki, Method of forming a via hole in a semiconductor device.
  18. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  19. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  20. Leu, Jihperng; Thomas, Christopher D., Method of making semiconductor device using an interconnect.
  21. Ning, Xian J., Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation.
  22. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
  23. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  24. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  25. Hussein Makarem A., Process to manufacture continuous metal interconnects.
  26. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  27. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  28. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  29. Nogami, Takeshi; Komai, Naoki; Kito, Hideyuki; Taguchi, Mitsuru, Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof.
  30. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  31. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.
  32. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  33. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (19)

  1. Lee, Hsien-Ming; Tsai, Minghsing; Jang, Syun-Ming, Approach for reducing copper line resistivity.
  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  3. Chen,Ling; Chang,Mei, Deposition processes for tungsten-containing barrier layers.
  4. Brain, Ruth A., Etchstop layers and capacitors.
  5. Johnston,Steven W.; Dubin,Valery M.; McSwiney,Michael L.; Moon,Peter, Forming a copper diffusion barrier.
  6. Wang,Xinming; Takagi,Daisuke; Tashiro,Akihiko; Fukunaga,Yukio; Fukunaga,Akira, Interconnects forming method and interconnects forming apparatus.
  7. Wang,Xinming; Takagi,Daisuke; Tashiro,Akihiko; Fukunaga,Yukio; Fukunaga,Akira, Interconnects forming method and interconnects forming apparatus.
  8. Choi, Hyung Bok; Park, Jong Bum; Lee, Kee Jeung; Lee, Jong Min, Method for fabricating capacitor of semiconductor device.
  9. Lin,Chin Hsiang, Method for photolithography in semiconductor manufacturing.
  10. Barabash, Sergey; Pramanik, Dipankar, Method of depositing films with narrow-band conductive properties.
  11. Preusse, Axel; Friedemann, Michael; Seidel, Robert; Freudenberg, Berit, Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime.
  12. Chang, Mei; Chen, Ling, Noble metal layer formation for copper film deposition.
  13. Chang,Mei; Chen,Ling, Noble metal layer formation for copper film deposition.
  14. Huang, Cheng-Lin, Reducing resistivity in interconnect structures of integrated circuits.
  15. Tsumura,Kazumichi; Usui,Takamasa, Semiconductor device and method for manufacturing the same.
  16. Tsumura,Kazumichi; Usui,Takamasa, Semiconductor device and method for manufacturing the same.
  17. Chang, Hui-Lin; Lu, Yung-Cheng; Jang, Syun-Ming, Synergy effect of alloying materials in interconnect structures.
  18. Chang, Hui-Lin; Lu, Yung-Cheng; Jang, Syun-Ming, Synergy effect of alloying materials in interconnect structures.
  19. Weiss, Martin; Brain, Ruth; Bigwood, Bob; Daviess, Shannon, Winged vias to increase overlay margin.
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