[특허]Massively parallel interface for electronic circuit

[미국특허] Massively parallel interface for electronic circuit 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-031/02 G01R-031/26
출원번호	US-0918511 (2004-08-12)
우선권정보	WO-PCT/US00/14768(2000-05-26)
발명자 / 주소	Chong,Fu Chiung Mok,Sammy
출원인 / 주소	NanoNexus, Inc.
대리인 / 주소	Glenn Patent Group
인용정보	피인용 횟수 : 28 인용 특허 : 157

초록 ▼

Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.

대표청구항 ▼

What is claimed is: 1. An apparatus for providing simultaneous electrical connections from an integrated circuit tester to an array of integrated circuit dice on a wafer, comprising: a plurality of interface modules, each of said interface modules comprising means for making simultaneous electrical connections to said dice; each of said interface modules further comprising a first planar region at a first end and a second planar region which extends said first end to a second end opposite said first end, said interface module comprising a plurality of electrically conductive pads disposed on sold first planar region for providing electrical connections to pads on said dice; and an interconnection link for providing an electrical connection to said tester at said second end and at least one electrical connection extending from at least one of said electrically conductive pads to said interconnection link; and a substrate having a probe surface and a connector surface, said probe surface having a plurality of probe contact tips for making simultaneous electrical contact to electrical contact pads of each of said integrated circuit dice, and a plurality of connections extending through said substrate between each of said plurality of said contact tips and said connector surface for interconnection with said electrically conducting pads; wherein said probe contact tips comprise a stress metal spring. 2. The apparatus of claim 1, wherein an average connection density of said electrically conductive pads disposed on said first planar region of said interface module is equal to or greater than an average pad density of said dice. 3. The apparatus of claim 1, each of said interface modules further comprising: a power control module; and at least one buss bar in electrical connection therewith. 4. The apparatus of claim 1, further comprising: means for holding each of said plurality of interface modules in physical alignment with said dice and for making simultaneous electrical connections to the pads of each die. 5. The apparatus of claim 1, further comprising at least one interposer. 6. The apparatus of claim 1, said probe contact tips comprising structures fabricated in a batch mode processes, comprising any of thin film microelectronic mechanical system processes.

이 특허에 인용된 특허 (157) 인용/피인용 타임라인 분석

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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Wafer-level test and burn-in, and semiconductor process.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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