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Debugging a program intended to execute on a reconfigurable device using a test feed-through configuration 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/44
출원번호 US-0055691 (2001-10-29)
발명자 / 주소
  • Andrade,Hugo A.
  • Odom,Brian Keith
  • Butler,Cary Paul
  • Peck,Joseph E.
  • Petersen,Newton G.
출원인 / 주소
  • National Instruments Corporation
대리인 / 주소
    Meyertons, Hood, Kivlin, Kowert &
인용정보 피인용 횟수 : 70  인용 특허 : 28

초록

A system and method for debugging a program which is intended to execute on a reconfigurable device. A computer system stores a program that specifies a function, and which is convertible into a hardware configuration program (HCP) and deployable onto a programmable hardware element comprised on the

대표청구항

We claim: 1. A system for debugging a program which is intended to execute on a reconfigurable device, the system comprising: a reconfigurable device, comprising: a programmable hardware element; and one or more fixed hardware resources coupled to the programmable hardware element; and a computer

이 특허에 인용된 특허 (28)

  1. Wright Adam, Apparatus and method for generating configuration and test files for programmable logic devices.
  2. Tredennick Harry L. (Los Gatos CA) Van den Bout David E. (Apex NC), Baseboard and daughtercard apparatus for reconfigurable computing systems.
  3. Shinde Hirotake (Kahoku JPX) Sugino Kazuhito (Kahoku JPX) Nakamichi Koji (Kahoku JPX) Matsubara Nozomu (Kahoku JPX) Hikono Atsushi (Kahoku JPX), Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and m.
  4. Beenstra Kerry ; Rangasayee Krishna ; Herrmann Alan L., Enhanced embedded logic analyzer.
  5. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  6. Kean Thomas A.,GB6 ITX EH88JQ ; Wilkie William A.,GB6 ITX EH106AP, FPGA with parallel and serial user interfaces.
  7. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA), Graphical system for modelling a process and associated method.
  8. Kodosky Jeffrey L. ; Truchard James J. ; MacCrisken John E., Graphical system for modelling a process and associated method.
  9. Taylor Brad (Oakland CA), Implementation of a selected instruction set CPU in programmable hardware.
  10. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  11. Kurosaka, Hitoshi, LSI verification method, LSI verification apparatus, and recording medium.
  12. Miller Keith (3490 Poppy St. Long Beach CA 90805), Light weight, self-contained programmable data-acquisition system.
  13. Lawman Gary R. ; Linoff Joseph D. ; Wasson Stephen L., Memory map computer control system for programmable ICS.
  14. Dangelo Carlos (Los Gatos CA) Watkins Daniel (Los Altos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  15. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  16. Sismilich Robert C. (Rockaway NJ), Method for using interactive computer graphics to control electronic instruments.
  17. Patterson, Cameron D.; Price, Timothy O., Parameterizable and reconfigurable debugger core generators.
  18. Taylor Brad (Oakland CA), Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication.
  19. Ledzius, Robert C.; Flemmons, James L.; Maturo, Lawrence R., Reconfigurable computing system and method and apparatus employing same.
  20. Tseng Ping-Sheng ; Lin Sharon Sheau-Pyng ; Shen Quincy Kun-Hsu ; Sun Richard Yachyang ; Tsai Mike Mon Yen ; Tsay Ren-Song ; Wang Steven, Simulation/emulation system and method.
  21. Devins, Robert J.; Kautzman, Mark E.; Mahler, Kenneth A.; Mitchell, William E., Simulator-independent system-on-chip verification methodology.
  22. Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  23. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
  24. Thomsen Carsten ; Kodosky Jeffrey L., System and method for providing audio probe and debugging features in a graphical data flow program.
  25. Pauna Mark R., System and method for simulation of integrated hardware and software components.
  26. Taylor Brad (Oakland CA) Dowling Robert (Albany CA), System for compiling algorithmic language source code for implementation in programmable hardware.
  27. Panchul Yuri V. ; Soderman Donald A. ; Coleman Denis R., System for converting hardware designs in high-level programming language to hardware implementations.
  28. Taylor Brad (Oakland CA), Video processing module using a second programmable logic device which reconfigures a first programmable logic device fo.

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  1. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Adaptive pattern recognition based controller apparatus and method and human-interface therefore.
  2. White, Jr., David C.; Mortensen, Magnus; Johnston, Jay K., Automatic classification and parallel processing of untested code in a protected runtime environment.
  3. Macklem, Grant V.; Wenzel, Lothar; Gosalia, Rishi H.; Juhasz, James T.; Dunia, Ricardo, Automatic conversion of a textual language into a graphical program representation.
  4. Robertsson, Per-Ola, Bi-directional probing and testing of software.
  5. Park, Hyun Ju, Chip design verification apparatus and data communication method for the same.
  6. Yamada, Kazuo, Circuit design information generating equipment, function execution system, and memory medium storing program.
  7. Cifra, Christopher G., Client side web hosted program development environment.
  8. Ghercioiu, Marius; Hedesiu, Horea; Folea, Silviu; Crisan, Gratian I.; Ceteras, Ciprian; Monoses, Ioan, Compact modular embedded device.
  9. Hudson, III, Duncan G.; Gosalia, Rishi H., Compiling a graphical program having a textual language program portion for a real time target.
  10. Kotzer, Igal; Riess, Eilon, Configurable communications module.
  11. Nelson, Craig A.; Fricke, Stephen J., Configurable input/output controller system.
  12. Kodosky, Jeffrey L.; Shah, Darshan; Rogers, Steven W., Configuration diagram with connections that represent physical couplings between devices.
  13. Kodosky, Jeffrey L.; Shah, Darshan; Rogers, Steven W., Configuration diagram with context sensitive connectivity.
  14. Kwong, Herman; Soh, Kah Ming; Handforth, Martin; Marcanti, Larry, Contact mapping using channel routing.
  15. Graf, Christopher F.; Brown, Ryan H.; Baker, Daniel J.; DeVoe, Matthew J.; Nagarajan, Sarvesh V., Customizing synchronization of custom code among multiple programmable hardware elements within a system.
  16. Moniz, Michael J.; Sheikh, Ali I.; Sutandie, Diana P.; Vijayakumar, Srivatsan; Zhang, Ying Di, Debugging optimized code using FAT binary.
  17. Akeel, Umair; Gordon, Justin Harding, Dependent object framework for junit testing and software application component.
  18. Dove, Andrew; Andrade, Hugo; Shah, Darshan, Distributed graphical program execution using a handheld computer.
  19. Brown, Ryan H.; Graf, Christopher F., Dynamic synchronization in a target system having multiple programmable hardware elements.
  20. Gosalia, Rishi H.; Attas, Jesse M.; Marker, Bryan A., Edit time analyzer in a loosely typed textual language.
  21. Legako,Michael R.; Berube,Darren R.; Annillo,Jonathan R., Embedded hardware debugging tool and associated method.
  22. Hodges, Stephen E.; Butler, David Alexander; Izadi, Shahram; Han, Chih-Chieh, Embedded system development platform.
  23. Hodges, Stephen E.; Butler, David Alexander; Izadi, Shahram; Han, Chih-Chieh, Embedded system development platform.
  24. Bisht, Ashutosh; Chaudhary, Abhijit, Flow and module level detecting and debugging with inclusion of generated log statements.
  25. Fournie,Jonathan P., Graphical programming system and method for creating and managing a scene graph.
  26. Breyer, John R., Graphical programs with direct memory access FIFO for controller/FPGA communications.
  27. Kornerup, Jacob; Kodosky, Jeffrey L.; Andrade, Hugo A.; Shah, Biren; Vrancic, Aljosa; Santori, Michael L., Graphically representing timing in a graphical program.
  28. Linebarger, Darel Allen; Englehart, Matthew; Szpak, Peter, Implicit reset.
  29. Leinfellner, Robert; Franzen, Ortwin Ludger; Limberg, Hans-Guenter; Dressler, Marc; Gruber, Paul, Influencing device for control apparatus.
  30. Chari, Srikumar; Jiang, Jason Yansheng; Namasivayam, Premchandar; Pathrikar, Swapnil, Integrated audit and configuration techniques.
  31. Gebhard, Derek Steven, Interactive application programming interface documentation.
  32. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Internet appliance system and method.
  33. Christensen, Erik B.; Coulson, Michael J.; Balayoghan, Vaithialingam B.; Iskin, Sermet, Metadata driven API development.
  34. Bhushan, Pranav; Chetput, Chandrashekar L.; O'Leary, Timothy Martin, Method and apparatus for AMS simulation of integrated circuit design.
  35. Bhushan, Pranav; Chetput, Chandrashekar L.; O'Leary, Timothy Martin, Method and apparatus for AMS simulation of integrated circuit design.
  36. Bhushan, Pranav; Chetput, Chandrashekar L.; O'Leary, Timothy Martin, Method and apparatus for AMS simulation of integrated circuit design.
  37. Kukal, Taranjit; Cheung, Chris; Kohli, Vikas; Felton, Keith; Farmar, Frank X.; Durrill, Steven R., Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout.
  38. Kukal, Taranjit; Durrill, Steven R., Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation.
  39. Adams, Gregory D; Bennett, Jonathan David; Giffen, Perry Randolph; Martens, Axel; O'Farrell, William Gerald, Method and system for state machine translation.
  40. Yamashita,Hiroyuki; Shinsha,Takao; Fujikake,Hideaki; Kowatari,Toshiaki; Hirao,Tomoya; Ohkuma,Atsushi; Nishi,Hiroaki; Muraoka,Michiaki, Method for co-verifying hardware and software for a semiconductor device.
  41. Tohdo,Tetsuya; Iwai,Akihito, Method, apparatus and program for testing control program.
  42. Graf, Christopher F.; Brown, Ryan H.; Baker, Daniel J.; DeVoe, Matthew J., Modifying a target system configuration to utilize a different synchronization module for performing synchronization among multiple programmable hardware elements.
  43. Allen, Timothy P.; Atsatt, Sean R.; Ball, James Loran, Modular processor debug core connection for programmable chip systems.
  44. Douskey, Steven M.; Gaurav, Raghu G.; Kusko, Mary P.; Rajeev, Hari K., Portion isolation architecture for chip isolation test.
  45. Hudson, III, Duncan G.; Gosalia, Rishi H., Providing target specific information for textual code at edit time.
  46. Smilg, Lawrence Mitchell; Ernst, James; Zeller, Robert, Reconfigurable FADEC with flash based FPGA control channel and ASIC sensor signal processor for aircraft engine control.
  47. Oota,Yoshiyuki, Self test device and self test method for reconfigurable device mounted board.
  48. Um, Taeho, Structurally-embedded construction, design, and maintenance record data management system and related method.
  49. Graf, Christopher F.; Brown, Ryan H.; Baker, Daniel J.; DeVoe, Matthew J., Synchronization modules for performing synchronization of programmable hardware elements.
  50. Graf, Christopher F.; Brown, Ryan H.; Baker, Daniel J.; DeVoe, Matthew J.; Nagarajan, Sarvesh V., Synchronization modules for programmable hardware and use.
  51. Donlin,Adam P., System and method for accessing signals of a user design in a programmable logic device.
  52. Holmes,Michael A.; Williams,Gerald S., System and method for automatically generating a hierarchical register consolidation structure.
  53. Tsai,Hung Yuan; Xiao,San; Zeng,Ge Xin, System and method for automatically testing motherboards.
  54. Bailie, Mark, System and method for communication between a programmer interface and an electronic device.
  55. Iotov, Mikhail; Starr, Greg, System and method for design entry and synthesis in programmable logic devices.
  56. Weigert, Thomas; Weil, Francis Joseph, System and method for implementing application code from application requirements.
  57. Alfieri, Robert Anthony, System, method, and computer program product for altering a line of code.
  58. Alfieri, Robert Anthony, System, method, and computer program product for applying a callback function to data values.
  59. Alfieri, Robert Anthony, System, method, and computer program product for constructing a data flow and identifying a construct.
  60. Alfieri, Robert Anthony, System, method, and computer program product for translating a common hardware database into a logic code model.
  61. Alfieri, Robert Anthony, System, method, and computer program product for translating a hardware language into a source database.
  62. Alfieri, Robert Anthony, System, method, and computer program product for translating a source database into a common hardware database.
  63. Englehart, Matthew, Systems and methods for modeling execution behavior.
  64. Englehart, Matthew J., Systems and methods for modeling execution behavior.
  65. Nagappan, Nachiappan; Bhat, Thirumalesh, Technologies for code failure proneness estimation.
  66. Ilic, Kosta; Blasig, Dustyn K., Testing a graphical program intended for a programmable hardware element.
  67. Kornerup, Jacob; Shah, Biren; Vrancic, Aljosa; Curtis, Matthew; Rogers, Steve, Timed loop with sequence frames structure for a graphical program.
  68. Kornerup, Jacob; Shah, Biren; Vrancic, Aljosa, Timed sequence for a graphical program.
  69. Newberry, Robert, Universal computer architecture.
  70. Moran, Tamir E.; Bains, Jatinderjit S.; Wertz, Daniel S., User-invoked calibration of modular system using an embedded calibration signal generator.
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