[미국특허]
Digital data system with link level message flow control
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/08
H04L-012/26
출원번호
US-0758949
(2001-01-11)
발명자
/ 주소
Frisch,Robert C.
Marietta,Bryan D.
Bouvier,Daniel L.
출원인 / 주소
Mercury Computer Systems, Inc.
대리인 / 주소
Nutter McClennen &
인용정보
피인용 횟수 :
18인용 특허 :
10
초록▼
A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed bet
A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed between adjacent nodes on a link to efficiently regulate message burden on the link. The control symbols may be embedded within in a message packet to quickly effect control on a link--such as reducing data flow, requesting retransmission of corrupted data, or other intervention--without disruption of the ongoing packet reception. A control symbol may be recognized within the packet by a flag bit, a marker such as a transition in a signal, or a combination of characteristics. The control symbol may be a short word, having a control action identifier code at defined bit positions to indicate the desired link-level control function. A node receiving the control symbol implements the designated control action while maintaining packet order data (such a bit positions and byte counts), and applying message housekeeping processing (such as error checking) as though the control symbol were absent. The control symbol is thus embedded in a manner such that a receiving node need not receive a complete message, or even a complete packet, before acting on the control symbol. The beginning and end of the interrupted packet, meanwhile, are handled as a single message packet, and are processed by the receiving node in properly-aligned bit positions, allowing message flow to continue along the link without interruption. Thus, retransmission of the affected packet or message is not required. The result is that control operations dictated by the embedded control symbol are effected immediately and without slowing down communications.
대표청구항▼
What is claimed is: 1. A digital data system comprising a plurality of nodes interconnected by at least one link, the nodes being configured to communicate message packets on the link, each message packet having a format and a plurality of symbols that are transmitted by a first node on the link a
What is claimed is: 1. A digital data system comprising a plurality of nodes interconnected by at least one link, the nodes being configured to communicate message packets on the link, each message packet having a format and a plurality of symbols that are transmitted by a first node on the link and received by a second node on the link, wherein the message packet is aligned in relation to a frame signal, at least one of said first and said second nodes being configured to communicate a link level control symbol, the link level control symbol being interposed between symbols of a message packet as an additional symbol to signal an adjacent node on the link, such that the adjacent node receives the additional symbol before completion of the message packet to effect a link level control of message flow on the link wherein said additional symbol is asserted with a marker whereby the adjacent node detects the control symbol within the message packet to effect said link level control of message flow wherein a node transmits the interposed control symbol in alignment with a symbol boundary in a message packet, whereby received data may be passed through a register of fixed size and the control symbol is discerned via the marker, permitting alignment of portions of a message packet irrespective of interposition of the control symbol therebetween. 2. A digital data system according to claim 1, wherein at least one node includes at least one of (i) an input buffer that at least temporarily stores a received message, and (ii) an output buffer that at least temporarily stores a message for transmission, and the control symbol effects a link level control to prevent buffer overflow. 3. A digital data system according to claim 1, wherein a message includes an error code for detecting corruption of a received message, and a receiving node that receives two portions of a message packet surrounding a control symbol realigns the received portions to apply the error code to the two portions of the message packet surrounding the control symbol. 4. A digital data system according to claim 3, where in the control symbol instructs the adjacent node to reduce its message transmission rate by transmitting a specified number of idle states so as to match receiver capacity to transmission rate. 5. A digital data system according to claim 1, wherein the control symbol instructs a receiving node to reduce its message transmission rate. 6. A digital data system according to claim 1, wherein the control symbol includes a control code for identifying one of i) a faulty message transmission, and ii) a faulty message reception. 7. A digital data system according to claim 1, wherein the link is bi-directional, and interconnects the first node at one end of the link with the second node at another end of the link, said first and second nodes being fl duplex nodes. 8. A digital data system according to claim 1, comprising a plurality of links forming an interconnect fabric among plural devices, the links interconnecting, and wherein each link has one node attached to one end of the link and another node attached to another end of the link, the nodes cooperating to route messages along interconnected links between the devices of the system.
Padovani, Roberto; Bender, Paul E.; Black, Peter J.; Grob, Matthew S.; Hinderling, Jurg K.; Sindhushayana, Nagabhushana T.; Wheatley, III, Charles E., Method and apparatus for high rate packet data transmission.
Arimilli, Ravi Kumar; Fields, Jr., James Stephen; Guthrie, Guy Lynn; Joyner, Jody Bern; Lewis, Jerry Don, Multi-node data processing system having a non-hierarchical interconnect architecture.
Pelley, III, Perry H.; Hoekstra, George P.; Pessoa, Lucio F., Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory.
Frodsham, Tim; Cherukuri, Naveen; Darbal, Sanjay; Dunning, David S.; Schoenborn, Theodore Z.; Krishnamurty, Lakshminarayan; Spink, Aaron T., Method, apparatus, and system for idle state definition for power management.
Engel, Yehiel; Ganor, Avraham; Horowitz, Tal; Schnarch, Michael Chaim; Shachar, Yaron; Weiser, Uri Chanan, Systems and methods for efficient handling of data traffic and processing within a processing device.
Engel, Yehiel; Ganor, Avraham; Horowitz, Tal; Schnarch, Michael Chaim; Shachar, Yaron; Weiser, Uri Chanan, Systems and methods for efficient handling of data traffic and processing within a processing device.
Engel, Yehiel; Ganor, Avraham; Horowitz, Tal; Schnarch, Michael Chaim; Shachar, Yaron; Weiser, Uri Chanan, Systems and methods for efficient handling of data traffic and processing within a processing device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.