초록 ▼

An object of the present invention is to make it possible to effect a reliable and compact configuration for a semiconductor device when mounting a plurality of semiconductor elements in a single package, and achieve higher integration and higher functionality more effectively. In a multi-layer wir

An object of the present invention is to make it possible to effect a reliable and compact configuration for a semiconductor device when mounting a plurality of semiconductor elements in a single package, and achieve higher integration and higher functionality more effectively. In a multi-layer wiring board 20 in which wiring patterns (conductor layers) 22, 24, and 26, and insulating layers 23, 25, and 27, are formed alternately in multiple layers on a base substrate, and electrically connections are made between the wiring patterns through via holes VH1 and VH2, semiconductor elements 30 are imbedded and mounted inside the insulating layers 23, 25, and 27, and the semiconductor elements 30 are deployed so that they are electrically connected to wiring patterns that are covered by the insulating layers, and so that they are stacked up in a direction perpendicular to the planar dimension of the multi-layer wiring board 20.

대표청구항 ▼

What is claimed is: 1. A semiconductor device, comprising: a first insulating layer having vias extending therethrough; a first conductive layer, comprising a first wiring pattern, embedded within the first insulating layer; a second conductive layer, comprising a second wiring pattern, formed on

What is claimed is: 1. A semiconductor device, comprising: a first insulating layer having vias extending therethrough; a first conductive layer, comprising a first wiring pattern, embedded within the first insulating layer; a second conductive layer, comprising a second wiring pattern, formed on the first insulating layer, the wiring pattern of the second conductive layer being electrically connected to the wiring pattern of the first conductive layer through the vias of the first insulating layer; a semiconductor element embedded in the first insulating layer and electrically connected to the wiring pattern of the first conductive layer; and a second insulating layer having a semiconductor element, electrically connected to the wiring pattern of the second conductive layer, embedded therein and embedding further therein the second conductive layer. 2. The semiconductor device according to claim 1, wherein one or more of the wiring patterns of the first conductive layer is/are electrically connected to one or more of the wiring patterns of the second conductive layer through corresponding said vias. 3. A semiconductor device, comprising: a substrate; a first set of conductors comprising a first conductive layer formed on the substrate; a first insulating layer formed on the first set of conductors and having vias extending therethrough, the first insulating layer having at least one semiconductor element and the first set of conductors embedded therein; a second set of conductors comprising a second conductive layer formed on the first insulating layer and extending through vias therein; and a second insulating layer formed on the second set of conductors and having vias extending therethrough, the second insulating layer having at least one semiconductor element and portions of the second set of conductors embedded therein; wherein one or more of the first set of conductors is/are electrically connected to the at least one semiconductor element embedded in the first insulating layer and one or more of the second set of conductors is/are electrically connected to the at least one semiconductor element embedded in the second insulating layer and through corresponding said vias to one or more of the first set of conductors.