[특허]Semiconductor multi-package module having wire bond interconnect between stacked packages

[미국특허] Semiconductor multi-package module having wire bond interconnect between stacked packages 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/02
출원번호	US-0632549 (2003-08-02)
발명자 / 주소	Karnezos,Marcos
출원인 / 주소	ChipPAC, Inc.
대리인 / 주소	Haynes Beffel &
인용정보	피인용 횟수 : 74 인용 특허 : 40

초록 ▼

A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

대표청구항 ▼

I claim: 1. A multi-package module comprising stacked lower and upper packages, the upper said package comprising an upper package die attached to and electrically interconnected to a die attach side of an upper package substrate and the lower said package comprising a lower package die attached to and electrically interconnected to a die attach side of a lower package substrate, each package substrate including at least one metal layer and at least one dielectric layer, and each package substrate being configured to provide electrical contact with said metal layer at the side of the substrate opposite the die attach side, the module further comprising second-level interconnection solder ball pads at the lower side of the lower package substrate, wherein the electrical interconnections between each said die and said substrate is protected, and wherein the upper and lower substrates are interconnected by wire bonding. 2. The multipackage module of claim 1 wherein at least one said package has wire bond interconnect of the die with the substrate and wherein said wire bond interconnect is protected by encapsulation. 3. The multi package module of claim 2 wherein the said package is fully encapsulated. 4. The multipackage module of claim 2 wherein the said package is encapsulated only to an extent sufficient to protect the wire bonds between the die and the substrate. 5. The multipackage module of claim 1 wherein at least one said package is a ball grid array package. 6. The multipackage module of claim 1 wherein at least one said package is a land grid array package. 7. The multipackage module of claim 1 wherein at least one said package has flip chip interconnect of the die with the substrate, and wherein the flip chip interconnect is protected by an underfill. 8. The multipackage module of claim 1, further comprising a heat spreader. 9. The multipackagc module of claim 1, further comprising an electromagnetic shield for at least one of the packages. 10. The multipackage module of claim 1 comprising a third stacked package.

이 특허에 인용된 특허 (40) 인용/피인용 타임라인 분석

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[미국특허] Semiconductor multi-package module having wire bond interconnect between stacked packages 원문보기

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[미국특허] Semiconductor multi-package module having wire bond interconnect between stacked packages 원문보기

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