A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes a plurality of multiply-accumulation blocks (40) which are operable to receive the signal and compare the received signal with a Walsh-Ha
A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes a plurality of multiply-accumulation blocks (40) which are operable to receive the signal and compare the received signal with a Walsh-Hadamard code. The comparison and the accumulation is made only in the middle of a chip clock with the edges thereof blanked. This information in the middle of the chip clock is accumulated in an accumulator, the MAC (40), for a symbol period. This is then compared with a look up table and then a decision made as to the logic value thereof.
대표청구항▼
What is claimed is: 1. A CDMA decoder for decoding a CDMA encoded signal from a desired CDMA channel, comprising: a receive input for receiving a CDMA encoded signal; a code generator for generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal en
What is claimed is: 1. A CDMA decoder for decoding a CDMA encoded signal from a desired CDMA channel, comprising: a receive input for receiving a CDMA encoded signal; a code generator for generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal encoded with a corresponding CDMA code transmitted over the predetermined CDMA channel; a multiply or accumulate device including a multiplication device for multiplying said received signal received on said receive input by said predetermined CDMA code word and operating in the analog domain, said multiply or accumulate device also including an accumulator operable to accumulate the results of the multiplication operation over a symbol period to provide an analog result; a data conversion device for determining if the analog result corresponds to a predetermined digital state and, if so, generating a digital output corresponding to said predetermined digital state; and a summation device for subtracting the output of said multiplication device from said analog result of said multiply or accumulate device prior to input to said data conversion device associated with said multiply or accumulate device. 2. The CDMA decoder of claim 1, wherein said predetermined digital state comprises multiple predetermined digital states and wherein said data conversion device is operable to generate multiple digital output states corresponding to the one of said multiple predetermined digital states to which the analog result has been determined to correspond. 3. The CDMA decoder of claim 2, wherein said multiple predetermined digital stats correspond to a "+1" logic state, a "0" logic state and a "-1" logic state. 4. The CDMA decoder of claim 1, wherein said data conversion device, by the operation of generating said digital output, provides a correlation of said encoded signal with said generated code word for said CDMA channel. 5. The CDMA decoder of claim 1, wherein said code generator operates in synchronization with a chip clock such that said predetermined CDMA code word is clocked by said chip clock, which chip clock changes from one logic state to a second logic state, and said multiply or accumulate device further including a blanking device for blanking the operation of said multiply or accumulate device during at least one of the leading or lagging edges of said chip clock at said one logic state for a predetermined blanking duration during which the operation of said multiply or accumulate device is inhibited to prevent accumulation of information therefrom. 6. The CDMA decoder of claim 5, wherein said blanking device operates during said leading and lagging edges of the chip clock. 7. The CDMA decoder of claim 1, and further comprising a blanking device for blanking the operation of said multiply or accumulate device for at least one of the leading or the lagging edges of said received signal for a predetermined blanking duration when transitioning between logic states. 8. The CDMA decoder of claim 7, wherein said blanking device is operable to blank said operation of said device for both said leading and lagging edges for said predetermined blanking duration. 9. The CDMA decoder of claim 1, wherein said code generator is operable to generate a plurality of CDMA codes, each associated with one of a plurality of CDMA channels such that said received input can receive a plurality of CDMA encoded signals each on a different channel and further comprising a plurality of multiply or accumulate devices, one for each channel and for each code word generated by said code generator and wherein said data conversion device is operable to determine for each of the multiply or accumulate devices if the associated analog result corresponds to said predetermined digital state and if so, generating a digital output corresponding to the associated multiply or accumulate devices such that a digital output is provided for each of said multiply or accumulate devices. 10. A CDMA decoder for decoding a CDMA encoded signal from a desired CDMA channel, comprising a receiving input for receiving a CDMA encoded signal; a code generator for generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal encoded with a corresponding CDMA code transmitted over the predetermined CDMA channel, said code generator operable to generate a plurality of CDMA codes, each associated with one of a plurality of CDMA channels such that said received input can receive a plurality of CDMA encoded signals each on a different channel; a data conversion device for determining if the analog result corresponds to a predetermined digital state and, if so, generating a digital output corresponding to said predetermined digital state; a plurality of multiply or accumulate devices, one for each channel and for each code word generated by said code generator and wherein said data conversion device is operable to determine for each of the multiply or accumulate devices if the associated analog result corresponds to said predetermined digital state and if so, generating a digital output corresponding to the associated multiply/accumulation device such that a digital output is provided for each of said multiply or accumulate devices; further comprising a subtraction device for subtracting from the analog result output from each of said multiply or accumulate devices contributions from signals on selective ones of the other channels encoded with their associated CDMA codes. 11. The CDMA decoder of claim 10, wherein said subtraction device comprises: a table device for storing defined predetermined relationships between the output of each of said multiply or accumulate devices for a signal input thereto on its associated channel and the output therefrom for signals input thereto for selected other channels, said relationship comprising a scale factor for the analog result; a multiplication device associated with each of said multiplication devices for multiplying the determined digital state from the other of said selected channels output by said associated data conversion device from said multiply or accumulate devices for said selected other channels; and a summation device for subtracting the output of each of said multiplication devices from said analog result of said each multiply or accumulate device prior to input to said data conversion device associated with said each multiply or accumulate device. 12. The CDMA decoder of claim 10, and further comprising an automatic gain control device for adjusting the gain of each of said multiply or accumulate devices. 13. The CDMA decoder of claim 12, further comprising an automatic gain control device for adjusting the gain of each of said multiply or accumulate device, wherein said automatic gain control device comprises: a multiplexer device for operating in a calibration mode and selecting one of said code words generated by said code generator associated with a reference one of the CDMA channels for input to each of said multiply/accumulation devices; a gain control device for adjusting the gain on the output of each of said multiply or accumulate devices such that, for the signal received on the reference one of the CDMA channels associated with the given one of said code words, the output signal level can be adjusted to a substantially similar level compared to the remaining multiply or accumulate devices. 14. The CDMA decoder for decoding a CDMA encoded signal from a desired CDMA channel, comprising: a receive input for receiving a CDMA encoded signal; a code generator for generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal encoded with a corresponding CDMA code transmitted over the predetermined CDMA channel; a multiply or accumulate device for multiplying said received signal received on said receive input by said predetermined CDMA code and operating in the analog domain, said multiply or accumulate device operable to accumulate the results of the multiplication operation over a symbol period to provide an analog result; and a data conversion device for determining if the analog result corresponds to a predetermined digital state and, is so, generating a digital output corresponding to said predetermined digital state; wherein said multiply or accumulate device comprises: at least one series leg including first and second series connected transistors disposed between a first node and a second reference voltage, said first transistor having the gate thereof connected to the received signal on said receive input and the gate of said second transistor connected to receive said code; a storage device connected to said first node; a precharge device for enabling said first node to be precharged to a defined level prior to the initiation of the accumulation operation at the beginning of a symbol period; and wherein said first and second transistors provide a multiplication operation or said code word and the received signal and said storage device is operable to accumulate the results of the multiplication operation over a symbol period. 15. The CDMA decoder of claim 14, wherein said multiply or accumulate device operates in a differential mode and further comprising a second leg comprised of first and second transistors connected in series between a second node an said reference voltage. 16. A method for decoding a CDMA encoded signal from a desired CDMA channel, comprising the steps of: receiving the CDMA encoded signal on a receive input; generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal encoded with a corresponding CDMA code transmitted over the predetermined CDMA channel; providing a multiply/accumulate device including a data conversion device and a multiplication device multiplying the received signal received on the receive input by the predetermined CDMA code in the analog domain and accumulating the result of the multiplying over a symbol period to provide an analog result; determining if the analog result corresponds to a predetermined digital state; and providing a summation device for subtracting the output of said multiplication devices from said analog result of said multiply or accumulate device prior to input to said data conversion device associated with said multiply/accumulate device. 17. The method of claim 16, wherein the predetermined digital state comprises multiple predetermined digital states, and wherein the step of generating a digital output is operable to generate multiple digital output states, each corresponding to the one of the multiple predetermined digital states to which the analog result has been determined to correspond. 18. The method of claim 16, wherein the step of generating the CDMA code is operable to generate a sequence of logic states that are synchronized with a chip clock such that the predetermined CDMA code is comprised of a plurality of logic states that are clocked by the chip clock, which chip clock changes from one logic state to a second logic state and the step of multiplying and the step of accumulating further including the step of blanking the operation of multiplying and accumulating during at least one of the leading or lagging edges of the chip clock at the one logic state for a predetermined blanking duration during which the multiplying and accumulation steps are inhibited to prevent accumulation of information therefrom. 19. The method of claim 18, wherein the step of blanking operates only during the leading and lagging edges of the chip clock. 20. The method of claim 16, wherein the step of generating the predetermined CDMA code is operable to generate a plurality of CDMA codes, each associated with one of a plurality of CDMA channels such that the receive input can receive a plurality of CDMA encoded signals each on a different channel and further comprising the step of providing a plurality of multiply or accumulate devices, each for carrying out the multiplying and accumulation steps for a given one of the CDMA channels and wherein the step of determining for each of the multiply or accumulate devices is operable to determine if the associated analog result corresponds to the predetermined digital state and, if so, generating a digital output corresponding to the associated multiply or accumulate device such that a digital output is provided for each of the multiply or accumulate devices. 21. A method for decoding a CDMA encoded signal from a desired CDMA channel, comprising the steps of: receiving the CDMA encoded signal on a receive input; generating a predetermined CDMA code for a predetermined CDMA channel that corresponds to an encoded signal encoded with a corresponding CDMA code transmitted over the predetermined CDMA channel; multiplying in a multiplication operation the received signal received on the receive input by the predetermined CDMA code in the analog domain and accumulating the result of the multiplication operation over a symbol period to provide an analog result; determining if the analog result corresponds to a predetermined digital sate and, if so, generating a digital output corresponding to the predetermined digital state; wherein the step of generating the predetermined CDMA code is operable to generate a plurality of CDMA codes, each associated with one of a plurality of CDMA channels such that the receive input can receive a plurality of CDMA encoded signals, each signal on a different channel and further comprising the step of providing a plurality of multiply or accumulate devices, each for carrying out the multiplying and accumulation steps for a given one of the CDMA channels and wherein the step of determining for each of the multiply or accumulate devices is operable to determine if the associated analog result corresponds to the predetermined digital state and, if so, generating a digital output corresponding to the associated multiply or accumulate device such that a digital output is provided for each of the multiply or accumulate devices; further comprising the step of subtracting from the analog result output from each of the multiply or accumulate devices contributions from signals on selective ones of the other channels encoded with their associated CDMA codes.
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이 특허에 인용된 특허 (13)
Lomp Gary ; Kowalski John ; Ozluturk Fatih ; Silverberg Avi ; Regis Robert ; Luddy Michael ; Marra Alexander ; Jacques Alexander, Code division multiple access (CDMA) communication system.
Skinner ; deceased Gordon (late of Boulder CO by Margo Boodakian ; legal representative ) Harms Brian (Superior CO), Signal acquisition in a multi-user communication system using multiple walsh channels.
Gilhousen Klein S. (San Diego CA) Jacobs Irwin M. (La Jolla CA) Padovani Roberto (San Diego CA) Weaver ; Jr. Lindsay A. (San Diego CA) Viterbi Andrew J. (La Jolla CA), System and method for generating signal waveforms in a CDMA cellular telephone system.
Gilhousen Klein S. (San Diego CA) Jacobs Irwin M. (La Jolla CA) Padovani Roberto (San Diego CA) Weaver ; Jr. Lindsay A. (San Diego CA) Wheatley ; III Charles E. (Del Mar CA) Viterbi Andrew J. (La Jol, System and method for generating signal waveforms in a CDMA cellular telephone system.
Gilhousen Klein S. ; Jacobs Irwin M. ; Padovani Roberto ; Weaver ; Jr. Lindsay A. ; Wheatley ; III Charles E. ; Viterbi Andrew J., System and method for generating signal waveforms in a CDMA cellular telephone system.
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