초록 ▼

An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memor

An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.

대표청구항 ▼

What is claimed is: 1. A multiple memory controller system, comprising: at least two memory controllers for controlling a main memory, wherein a first of the at least two memory controllers is directly connected to a central processing unit bus, a bus supporting a peripheral device, and the main me

What is claimed is: 1. A multiple memory controller system, comprising: at least two memory controllers for controlling a main memory, wherein a first of the at least two memory controllers is directly connected to a central processing unit bus, a bus supporting a peripheral device, and the main memory, wherein each of the at least two memory controllers is configured to communicate with a central processing unit via the central processing unit bus, wherein each of the memory controllers are independent of the central processing unit, and also wherein the first of the at least two memory controllers comprises an accelerated graphics port for establishing a dedicated, point-to-point connection between the first of the at least two memory controllers and an accelerated graphics processor. 2. The system of claim 1, wherein the first of the at least two memory controllers defines a range of addresses in memory that are preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 3. The system of claim 1, wherein at least two of the at least two memory controllers are manufactured on the same chip. 4. The system of claim 1, wherein the first of the at least two memory controllers maintains a graphical address remapping table comprising at least one page table entry (PTE) providing information for translation of a virtual address to a physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the graphical address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address. 5. The system of claim 4, wherein the first portion comprises a virtual page number field. 6. The system of claim 4, wherein the second portion comprises an offset field. 7. The system of claim 4, wherein the graphical address remapping table is configured by loading at least one configuration register during boot up of a computer system. 8. The system of claim 7, additionally comprising one configuration register includes a starting address of the graphical address remapping table. 9. The system of claim 7, wherein the at least one configuration register includes a boundary address defining the lowest address of a graphical address remapping table range. 10. The system of claim 7, wherein the at least one configuration register includes a range register defining the amount of memory that is preferentially used over other addresses for storage of graphics data for accelerated graphic port transactions. 11. The system of claim 7, wherein an initialization BIOS loads the at least one configuration register. 12. The system of claim 7, wherein an operating system API loads the at least one configuration register. 13. The system of claim 1, wherein the one of the at least two memory controllers and a memory are on a single semiconductor chip. 14. A computer, comprising: at least one accelerated graphics processor; and at least two memory controllers for controlling a main memory, wherein a first of the at least two memory controllers is directly connected to a central processing unit bus, a bus supporting a peripheral device, and the main memory, wherein each of the at least two memory controllers is configured to communicate with a central processing unit via the central processing unit bus, wherein each of the memory controllers are independent of the central processing unit, and wherein the first of the at least two memory controllers comprises an accelerated graphics port for establishing a dedicated point-to-point connection between the first of the at least two memory controllers and the accelerated graphics processor. 15. The system of claim 14, wherein the first of the at least two memory controllers defines a range of addresses that are preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 16. The computer of claim 14, wherein at least two of the at least two memory controllers include an accelerated graphics port. 17. The computer of claim 14, wherein at least two of the at least two memory controllers are included on the same chip. 18. The computer of claim 14, further comprising a graphical address remapping table residing on a memory connected to said first of the at least two memory controllers. 19. The computer of claim 18, wherein the graphical address remapping table is configured by loading at least one configuration register during boot up of a computer system. 20. The computer of claim 18, additionally comprising at least one configuration register that includes a starting address of the graphical address remapping table. 21. The computer of claim 18, wherein the at least one configuration register includes a boundary address defining the lowest address of a graphical address remapping table range. 22. The computer of claim 18, wherein an initialization BIOS loads the at least one configuration register. 23. The computer of claim 18, wherein an operating system API loads the at least one configuration register. 24. The computer of claim 14, further comprising a graphical address remapping table residing on said first of the at least two memory controllers, wherein the graphical address remapping table comprises at least one page table entry (PTE) providing information for translation of a virtual address to a physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the graphical address remapping table and wherein the second portion and the information provided by the PTE are combined to provide the physical address. 25. The computer of claim 14, wherein the first portion comprises a virtual page number field. 26. The computer of claim 14, wherein the second portion comprises an offset field. 27. The computer of claim 14, wherein said first of the at least two memory controllers and a memory are on a single semiconductor chip. 28. A multiple memory controller computer comprising: means for transmitting data to at least two memory controllers that each control a main memory wherein a first of the at least two memory controllers is directly connected to a central processing unit bus, a bus supporting a peripheral device, and the main memory, and wherein each of the at least two memory controllers is configured to communicate with a central processing unit via the central processing unit bus, wherein each of the memory controllers are independent of the central processing unit; and means for providing a dedicated point-to-point connection between a graphics accelerator and a first of the at least two memory controllers. 29. The computer of claim 28, and wherein the first of the at least two memory controllers defines a range of addresses that is preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 30. The computer of claim 28, further comprising means for controlling a graphical address remapping table having at least one page table entry (PTE) providing information for a translation of a virtual address to a physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the graphical address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address. 31. The computer of claim 30, wherein the first portion comprises a virtual page number field. 32. The computer of claim 30, wherein the second portion comprises an offset field. 33. The computer of claim 30, wherein the physical address references a location in a memory. 34. The computer of claim 33, wherein an initialization BIOS loads said at least one configuration register. 35. The computer of claim 33, wherein an operating system API loads said at least one configuration register. 36. The computer of claim 30, wherein the graphical address remapping table is configured by loading said at least one configuration register during boot up of a computer system. 37. The computer of claim 28, additionally comprising at least one configuration register that includes a starting address of the graphical address remapping table. 38. The computer of claim 35, wherein the at least one configuration register includes a boundary address defining the lowest address of a graphical address relocation table range. 39. The computer of claim 35, wherein said at least one configuration register includes a range register defining the amount of memory that is preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 40. A method of using a multiple memory controller computer, comprising: controlling a main memory with at least two memory controllers, wherein a first memory controller is connected to an accelerated graphics processor via a dedicated point-to-point connection, and wherein the first of the at least two memory controllers is directly connected to a central processing unit bus, a bus supporting a peripheral device, and the main memory, wherein each of the at least two memory controllers is configured to communicate with a central processing unit via the central processing unit bus, wherein each of the memory controllers are independent of the central processing unit; and defining a group of addresses in the main memory that are preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 41. The method of claim 40, further comprising the act of controlling a graphical address remapping table having at least one page table entry (PTE) which provides information for a translation of a virtual address to a physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the graphical address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address. 42. The method of claim 41, further comprising allocating a virtual page number field to the first portion. 43. The method of claim 41, further comprising allocating an offset field to the second portion. 44. The method of claim 41, further comprising loading said at least one configuration register during boot up of a computer system. 45. The method of claim 44, further comprising defining in a base address register the starting point of memory preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 46. The method of claim 44, further comprising setting a boundary address register defining the lowest address of the graphical address remapping table. 47. The method of claim 44, further comprising using a range register in the at least one configuration register to define the amount of memory that is preferentially used over other addresses for storage of graphics data for transactions associated with the dedicated point-to-point connection. 48. The method of claim 44, further comprising using an initialization BIOS to load said at least one configuration register. 49. The method of claim 44, further comprising using the operating system API to load said at least one configuration register. 50. The method of claim 40, further comprising manufacturing said at least two memory controllers and a memory on a single semiconductor chip.