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Method for inserting objects into a working area in a computer application 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G09G-005/00
  • G06F-009/45
출원번호 US-0856972 (1998-11-30)
국제출원번호 PCT/SE98/002183 (1998-11-30)
§371/§102 date 20010629 (20010629)
국제공개번호 WO00/033173 (2000-06-08)
발명자 / 주소
  • Ternulf,Yngve
  • Pourmakhdomi,Shahram
  • Otreus,Finn
출원인 / 주소
  • Actcon Control AB
대리인 / 주소
    Birch, Stewart, Kolasch &
인용정보 피인용 횟수 : 4  인용 특허 : 44

초록

The present invention relates to a method for facilitating the insertion of an object in a working area on a computer display, and is implemented in a computer application software. The method comprises the steps of indicating at least one subarea of the working area where an object is insertable, i

대표청구항

What is claimed is: 1. A method for creating a logical network by inserting a plurality of objects into a working area on a computer display, comprising the steps of: displaying an existing network in said working area; identifying at least one subarea of the working area where an object is validly

이 특허에 인용된 특허 (44)

  1. Julian Culetu ; Chaim Amir, Apparatus and method for inserting repeaters into a complex integrated circuit.
  2. Katoh Katsumi,JPX ; Jinguji Kaname,JPX, Circuit design system, image processing method and medium of the circuit design system.
  3. Rowson James A. (Fremont CA), Circuit simulation interface methods.
  4. Goto Kazunari,JPX, Circuit simulation model extracting method and device.
  5. Lawman Gary R. (San Jose CA) Wells Robert W. (Cupertino CA), Concurrent electronic circuit design and implementation.
  6. William Wai Yan Ho, Connectivity-based approach for extracting layout parasitics.
  7. Korszun Henry A. (302 Lexington Ave. New Haven CT 06513), Digital dressing room.
  8. Mankin Richard A. (Medway MA) Allen David L. (Maynard MA) Deshmukh Prasanna P. (Northboro MA), Electronic circuit design system and method with programmable addition and manipulation of logic elements surrounding te.
  9. Sato Shinichiro (Fussa JPX) Kojo Takashi (Ome JPX) Murata Yoshiyuki (Ome JPX), Electronic montage composing apparatus.
  10. Yoshino Hiroyuki (Higashiyamato JPX) Kojo Takashi (Ome JPX), Electronic montage creation device.
  11. Shugar Joel K. (303 Nigara Falls Blvd. Buffalo NY 14226) Cohen Robert k. (244 Hansen Ave. Albany NY 12208), Finite element modeling system.
  12. Nakamura Takeo (Kawasaki JPX) Yamada Syuichiro (Kawasaki JPX) Yoshida Yasuko (Kawasaki JPX), Graphic editor.
  13. Cariffe Alan E. ; Woodson Anne-Marie, Graphical user interface for image editing.
  14. Kobayashi Hideaki (Columbia SC) Shindo Masahiro (Osaka JPX), Knowledge based method and apparatus for designing integrated circuits using functional specifications.
  15. Tawada Shigeyoshi,JPX, Layout design apparatus.
  16. John R. Koza ; Forrest H Bennett, III ; David Andre ; Martin A. Keane, Method and apparatus for automated design of complex structures using genetic programming.
  17. Williams, Anthony D., Method and apparatus for developing and placing a circuit design.
  18. Oshima Sayuri (Kanagawa JPX) Nakajima Akira (Tokyo JPX) Naito Akira (Kanagawa JPX) Matsuda Yasumasa (Tokyo JPX) Endo Hirohide (Saitama JPX) Mese Michihiro (Kanagawa JPX) Yamauchi Tsukasa (Kanagawa JP, Method and apparatus for generating graphics.
  19. Owens David H. (Los Altos CA) Fisher Stephen (Menlo Park CA), Method and apparatus for improved application program switching on a computer-controlled display system.
  20. Thomas L. Quarles ; S. Peter Liebmann ; Leslie D. Spruiell, Method and apparatus for improvement of sparse matrix evaluation performance.
  21. Silver William M. (Medfield MA) Druker Samuel (Brookline MA) Romanik Philip (West Haven CT) Arbogast Carroll (Needham MA), Method and apparatus for interactively generating a computer program for machine vision analysis of an object.
  22. Yaacov (Jacob) Greidinger ; Ara Markosian ; Jon Frankle, Method and apparatus for providing multiple electronic design solutions.
  23. Sato Kenichi,JPX ; Shirota Norihisa,JPX ; Iida Yasuhiro,JPX ; Sasano Mitsuru,JPX, Method and apparatus for the design of a circuit.
  24. Maeda Koji,JPX, Method and apparatus for verifying and electrical configuaration using a psuedo-element pattern.
  25. Yun Chae-Won,KRX, Method and device for producing automatic insertion path in apparatus for automatically inserting electronic components into printed circuit board.
  26. Gioello, Debbie A., Method for designing apparel.
  27. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.
  28. Goetting F. Erich, Method for providing placement information during design entry.
  29. Wright John H. (Scotts Valley CA) Tomas Stephen P. (Sunnyvale CA), Method for specifying and controlling the invocation of a computer program.
  30. Groeneveld Patrick R. ; van Ginneken Lukas P. P. P., Method of designing a constraint-driven integrated circuit layout.
  31. Hernandez Irene H. (Austin TX) Himelstein Carol S. (Austin TX) Wang John S. (Austin TX), Method of editing graphic objects in an interactive draw graphic system using implicit editing actions.
  32. Maziasz Robert L. ; Guruswamy Mohankumar ; Raman Srilata, Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors.
  33. Yoshiyuki Murata JP, Object image display devices.
  34. Cohn John M. (Richmond VT) Heng Fook-Luen (Yorktown Heights NY), Object placement aid.
  35. Lewis Robert W. ; Tanner Matthew A. ; Walker Timothy K., Object-oriented computer program, system, and method for developing control schemes for facilities.
  36. Makino Satoru,JPX ; Takeda Yumiko,JPX ; Kawai Mina,JPX, Portrait drawing apparatus.
  37. Spackova, Daniela S.; Chen, Richard M., Previewer.
  38. Karchmer David ; Redman Scott D. ; Chen Jeffrey ; Schleicher James, Programmable logic array device design using parameterized logic modules.
  39. Yamanouchi Takayuki,JPX, Routing design method and routing design apparatus.
  40. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Rule structure for insertion of new elements in a circuit design synthesis procedure.
  41. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Rule structure in a procedure for synthesis of logic circuits.
  42. Miller John A. (Wilmette IL) Cleven David R. (Algonquin IL) Wall Robert J. (Highland Park IL), User specific intelligent interface which intercepts and either replaces or passes commands to a data identity and the f.
  43. Rom Ehud,ILX, Virtual dressing over the internet.
  44. Rubin Robert V. ; Sneddon Steven L., Visual programming tool for developing software applications.

이 특허를 인용한 특허 (4)

  1. Gotz, David Haim, Generating animated voronoi treemaps to visualize dynamic hierarchical data with node insertion.
  2. Welicki, Leon Ezequiel; Wang, Mo; Scrosati, Christopher; Owens, Kristofer John; Harris, Jon; Sterling, Jonah Bush; Supino, Dina-Marie Ledonna; Joshi, Vishal R.; Francisco, Jesse David; Danton, Stephen Michael, Organization mode support mechanisms.
  3. Takahashi,Susumu; Yanagimoto,Takashi; Kon,Tetsuo; Misaki,Tsuneo, Product design support system, product design support method, and program.
  4. Danton, Stephen M.; Roberts, Scott; Mollicone, Laurent; Sehn, Jordan; Price, Tad D.; Peck, David K.; Rychikhin, Yuri, Using visual landmarks to organize diagrams.
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