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Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that a

Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

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What is claimed is: 1. A method for constructing an electrical interconnect having enhanced mechanical properties on a semiconductor substrate, comprising: formation of a first recess in an electrically-insulating material; deposition of a first electrically-conductive material in the first recess

What is claimed is: 1. A method for constructing an electrical interconnect having enhanced mechanical properties on a semiconductor substrate, comprising: formation of a first recess in an electrically-insulating material; deposition of a first electrically-conductive material in the first recess, wherein said first electrically-conducting material comprises a metal; formation of a second recess in the first electrically-conductive material; and deposition of a second electrically-conductive material in the second recess in direct contact with the first electrically-conductive material, wherein said second electrically-conducting material comprises an alloy of copper and arsenic. 2. The method of claim 1, wherein the second electrically-conductive material is deposited by electroless plating. 3. The method of claim 2, wherein the depth of the second recess is in the range of about 50 to about 500 Angstroms. 4. The method of claim 1, wherein copper is present in the second electrically-conductive material at a concentration of between about 95 and about 99.9 weight percent. 5. The method of claim 1, wherein the deposition of the second electrically-conductive material by a vapor deposition technique. 6. The method of claim 1, wherein the formation of the second recess results at least in part from chemically etching the first electrically-conductive material. 7. The method of claim 1, wherein the formation of the second recess results at least in part from over polishing during a chemical mechanical polish ("CMP") step. 8. The method of claim 1, wherein the first recess comprises a secondary trench overlying a primary trench and wherein the second recess in the first conductive material is located primarily above the primary trench. 9. A method for constructing an electrical interconnect having enhanced mechanical properties on a semiconductor substrate, comprising: formation of a first recess in an electrically-insulating material; deposition of a thin seed layer of a first electrically-conductive material in the first recess; deposition of a second electrically-conductive material in the first recess, wherein said second electrically-conductive material comprises a metal; chemical-mechanical polish of said second electrically-conductive material; after said chemical-mechanical polish, formation of a second recess in the second electrically-conductive material by etching; and deposition of a third electrically-conductive material in the second recess in direct contact with said second electrically-conductive material, wherein said third electrically-conductive material comprises an alloy including said metal. 10. The method of claim 9, wherein the deposition of the thin seed layer occurs by electroless plating. 11. The method of claim 9, wherein the deposition of the third electrically-conductive material occurs by electroless plating. 12. The method of claim 10, wherein the thin seed layer has a thickness in the range of about 10 to about 50 Angstroms. 13. The method of claim 10, wherein the first and third electrically-conductive materials comprise copper and a material selected from the group consisting of arsenic, antimony, chromium, palladium, tin, magnesium, aluminum, cobalt, and zirconium. 14. The method of claim 13, wherein the first and the third electrically-conductive materials contain an amount of non-copper material in the range of about 0.1 to about 10.0 percent by weight. 15. The method of claim 10, wherein the second recess has a depth in the range of about 50 to about 500 Angstroms. 16. The method of claim 9, wherein the deposition of the thin seed layer occurs by atomic layer growth. 17. The method of claim 9, wherein the first recess comprises a secondary trench overlying a primary trench and wherein the second recess is located primarily above the primary trench.