IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0861112
(2001-05-18)
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발명자
/ 주소 |
- Dao,Khang Kim
- Baxter,Glenn A.
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
55 인용 특허 :
81 |
초록
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A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD. Finally, the functions of the processor local bus can be efficiently limited, thereby allowing the PLD to approach the performance level of an ASIC.
대표청구항
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What is claimed is: 1. A field programmable gate array (FPGA) having a central processing unit (CPU) provided therein, the FPGA comprising: an on-chip bus; a crosspoint switch generated by a core, wherein the crosspoint switch provides communication between the CPU and logic implemented on the FPGA
What is claimed is: 1. A field programmable gate array (FPGA) having a central processing unit (CPU) provided therein, the FPGA comprising: an on-chip bus; a crosspoint switch generated by a core, wherein the crosspoint switch provides communication between the CPU and logic implemented on the FPGA by way of the on-chip bus; and a high speed bus interface coupled between the crosspoint switch and a second bus, the high speed bus interface enabling the transfer of data to an off-chip device. 2. The FPGA of claim 1, wherein the CPU includes a master device and the logic includes a plurality of slave devices and a plurality of master devices. 3. The FPGA of claim 2, wherein the crosspoint switch selectively provides paths between the master devices and the slave devices. 4. The FPGA of claim 3, wherein the crosspoint switch includes: a plurality of address decoders for receiving addresses from the masters; and a plurality of access arbiters for receiving decoded addresses from the address decoders and for arbitrating transactions between the masters and the slaves. 5. The FPGA of claim 4, wherein the crosspoint switch provides full connectivity between the address decoders and the access arbiters. 6. The FPGA of claim 4, wherein connectivity between the address decoders and the access arbiters can be selectively changed. 7. The FPGA of claim 4, wherein the crosspoint switch includes: a plurality of write multiplexers for receiving write data from the masters, each write multiplexer selectively providing the write data to one slave; and a plurality of read multiplexers for receiving read data from the slaves, each read multiplexer selectively providing the read data to one master, wherein the write and read multiplexers are controlled by the plurality of access arbiters. 8. The FPGA of claim 7, wherein the crosspoint switch provides full connectivity between each write multiplexer and the plurality of master devices. 9. The FPGA of claim 7, wherein connectivity between each write multiplexer and the plurality of master devices can be selectively changed. 10. The FPGA of claim 7, wherein the crosspoint switch provides full connectivity between each read multiplexer and the plurality of slave devices. 11. The FPGA of claim 7, wherein connectivity between each read multiplexer and the plurality of slave devices can be selectively changed. 12. The FPGA of claim 3, wherein the paths include pipelining for queueing of transactions between the masters and slaves. 13. A field programmable gate array (FPGA) having an embedded microprocessor, the FPGA comprising: an on-chip bus; a plurality of master devices coupled to the on-chip bus, wherein the microprocessor is one such master device; a plurality of slave devices coupled to the on-chip bus; and means for selectively providing connectivity between the plurality of master devices and the plurality of slave devices by way of the on-chip bus, wherein the means for selectively providing connectivity is generated by a core; and means for providing connectivity to off-chip peripheral devices by way of a high speed bus interface coupled to a second bus. 14. The FPGA of claim 13, wherein the means for selectively providing full connectivity includes: means for decoding addresses from the master devices; and means for arbitrating transactions between the plurality of master devices and the plurality of slave devices based on the decoded addresses. 15. The FPGA of claim 14, wherein the means for selectively providing connectivity provides full connectivity between the means for decoding and the means for arbitrating. 16. The FPGA of claim 14, wherein connectivity between the means for decoding and the means for arbitrating can be selectively changed. 17. The FPGA of claim 14, wherein the means for selectively providing connectivity includes: means for receiving write data from the plurality of master devices and selectively providing the write data to designated slave devices; and means for receiving read data from the plurality of slave devices and selectively providing the read data to designated master devices, wherein the means for receiving write data and the means for receiving read data are controlled by the means for arbitrating. 18. The FPGA of claim 17, wherein the means for selectively providing connectivity provides full connectivity between the means for receiving write data and the plurality of master devices. 19. The FPGA of claim 17, wherein connectivity between the means for receiving write data and the plurality of master devices can be selectively changed. 20. The FPGA of claim 17, wherein the means for selectively providing connectivity provides full connectivity between the means for receiving read data and the plurality of slave devices. 21. The FPGA of claim 17, wherein connectivity between the means for receiving read data and the plurality of slave devices can be selectively changed. 22. The FPGA of claim 13, wherein the means for selectively providing connectivity includes means for queueing of transactions between the plurality of master devices and the plurality of slave devices. 23. A method of providing an interface between a central processing unit (CPU) on a programmable logic device (PLD) and user-implemented logic on the PLD, the method comprising: selectively providing connectivity, by way of a core designated by a user, between a plurality of master devices provided by the logic and a plurality of slave devices provided by the logic by way of an on-chip bus, wherein the CPU includes at least one master device; and selectively providing connectivity from the core designated by a user to off-chip peripheral devices by way of a high speed bus interface coupled to a second bus. 24. The method of claim 23, wherein the step of selectively providing connectivity includes: decoding addresses from the master devices using address decoders; and arbitrating transactions between the plurality of master devices and the plurality of slave devices using access arbiters and the decoded addresses. 25. The method of claim 24, wherein the step of selectively providing connectivity provides full connectivity between the address decoders and the access arbiters. 26. The method of claim 24, wherein the step of selectively providing connectivity provides less than full connectivity between the address decoders and the access arbiters. 27. The method of claim 24, wherein the step of selectively providing connectivity further includes: receiving write data from the plurality of master devices and selectively providing the write data to designated slave devices using a first set of multiplexers; and receiving read data from the plurality of slave devices and selectively providing the read data to designated master devices using a second set of multiplexers. 28. The method of claim 27, wherein the step of selectively providing connectivity provides full connectivity between the first set of multiplexers and the plurality of master devices. 29. The method of claim 27, wherein the step of selectively providing connectivity provides less than full connectivity between the first set of multiplexers and the plurality of master devices. 30. The method of claim 27, wherein the step of selectively providing connectivity provides full connectivity between the second set of multiplexers and the plurality of slave devices. 31. The method of claim 27, wherein the step of selectively providing connectivity provides less than full connectivity between the second set of multiplexers and the plurality of slave devices. 32. The FPGA of claim 23, wherein the step of selectively providing connectivity includes queueing transactions between the plurality of master devices and the plurality of slave devices. 33. A method of providing an interface between a central processing unit (CPU) on a programmable logic device (PLD) and user-implemented logic on the PLD, the method comprising: selecting a core from a library, wherein the core selectively provides connectivity between a plurality of master devices provided by the logic and a plurality of slave devices provided by the logic by way of an on-chip bus, wherein the CPU includes at least one master device and wherein the core provides connectivity to off-chip peripheral devices by way of a high speed bus interface coupled to a second bus. 34. The method of claim 33, further including setting at least one parameter in the core, thereby affecting the connectivity. 35. A field programmable gate array (FPGA) having a central processing unit (CPU) provided therein, the FPGA comprising: an on-chip bus; a hybrid switch generated by a core and coupled to the on-chip bus, wherein the hybrid switch provides communication between the CPU and logic implemented on the FPGA by way of the on-chip bus; and a high speed bus interface coupled between the hybrid switch and a second bus, the high speed bus interface enabling the transfer of data to an off-chip device. 36. The FPGA of claim 35, wherein the CPU includes a master device and the logic includes a plurality of slave devices and a plurality of master devices. 37. The FPGA of claim 36, wherein the hybrid switch includes crosspoint and shared bus configurations to provide paths between the master devices and the slave devices. 38. The FPGA of claim 37, wherein the hybrid switch includes: a plurality of address decoders for receiving addresses from the masters; and a plurality of access arbiters for receiving decoded addresses from the address decoders and for arbitrating transactions between the masters and the slaves, wherein at least one access arbiter provides the arbitration for more than one slave, and wherein at least one access arbiter provides arbitration for only one slave. 39. The FPGA of claim 38, wherein connectivity between the address decoders and the access arbiters can be selectively changed. 40. The FPGA of claim 37, wherein the hybrid switch includes: a plurality of write multiplexers for receiving write data from the masters and providing write data to the slave, wherein at least one write multiplexer provides its write data to more than one slave, and wherein at least one write multiplexer provides its write data to only one slave; and a plurality of read multiplexers for receiving read data from the slaves and selectively providing the read data to the masters. 41. The FPGA of claim 40, wherein at least one read multiplexer provides its read data to more than one master, and wherein at least one read multiplexer provides its read data to only one master. 42. The FPGA of claim 40, wherein the write and read multiplexers are controlled by the plurality of access arbiters. 43. The FPGA of claim 42, wherein connectivity between each write multiplexer and the plurality of master devices can be selectively changed. 44. The FPGA of claim 42, wherein connectivity between each read multiplexer and the plurality of slave devices can be selectively changed. 45. The FPGA of claim 35, wherein the hybrid switch includes pipelining for transactions between the masters and slaves.
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