초록 ▼

According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions ( 54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-n

According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions ( 54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

대표청구항 ▼

What is claimed is: 1. A very long instruction word (VLIW) processing core comprising: a processing pipeline having N-number of processing paths for processing an instruction comprising N-number of P-bit instructions appended together to form a VLIW, said N-number of processing paths process said N

What is claimed is: 1. A very long instruction word (VLIW) processing core comprising: a processing pipeline having N-number of processing paths for processing an instruction comprising N-number of P-bit instructions appended together to form a VLIW, said N-number of processing paths process said N-number of P-bit instructions in parallel on M-bit data words; and one or more register files having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide; wherein a first one of said Q-number of general purpose registers in at least one of said one or more register files is a dedicated program counter register which stores a current program counter value; wherein a second one of said Q-number of general purpose registers in said at least one of said one or more register files is hardwired to a set value; and wherein said processing core is fabricated on a single silicon die. 2. The processing core as recited in claim 1, wherein the second one of said Q-number of general purpose registers in at least one of said one or more register files is a zero register which always stores zero. 3. The processing core as recited in claim 1, wherein program jumps are executed by adding a value to the current program counter value stored in the program counter register using a standard add operation. 4. The processing core as recited in claim 1, wherein memory addresses are calculated by adding a value to the current program counter value stored in the program counter register using a standard add operation. 5. The processing core as recited in claim 1, wherein program jump tables hold values, which are offset values from the current program counter value. 6. The processor chip as recited in claim 1, wherein M=64, Q=64, and P=32. 7. The processing core as recited in claim 1, wherein said Q-number of general purpose registers within each of said one or more register files are either private or global registers, and wherein when a value is written to one of said Q-number of said registers which is a global register within one of said plurality of register files, said value is propagated to a corresponding global register in the other of said one or more register files, and wherein when a value is written to one of said Q-number of said registers which is a private register within one of said one or more register files, said value is not propagated to a corresponding register in the other of said one or more register files. 8. The processing core as recited in claim 7, wherein Q=64, and a 64-bit special register stores bits indicating whether a register in a register file is a private register or a global register, each bit in the 64-bit special register corresponding to one of said registers in said register file. 9. The very long instruction word (VLIW) processing core of claim 1, wherein said one or more register files are included within said processing pipeline. 10. A processing core comprising: a processing pipeline having N-number of processing paths, each of said processing paths for processing instructions on M-bit data words; and one or more register files, each having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide; wherein a first one of said Q-number of general purpose registers in at least one of said one or more register files is a dedicated program counter register which stores a current program counter value; wherein a second one of said Q-number of general purpose registers in said at least one of said one or more register files is hardwired to a set value; wherein said at least one of said one or more register files may be accessed by at least two of said N-number of processing paths; and wherein said Q-number of general purpose registers within each of said one or more register files are either private or global registers, and wherein when a value is written to one of said Q-number of said registers which is a global register within one of said one or more register files, said value is propagated to a corresponding global register in the other of said one or more register files, and wherein when a value is written to one of said Q-number of said registers which is a private register within one of said one or more register files, said value is not propagated to a corresponding register in the other of said one or more register files. 11. The processing core as recited in claim 10, wherein said second one of said Q-number of general purpose registers in at least one of said one or more register files is a zero register which always stores zero. 12. The processing core as recited in claim 10, wherein program jumps are executed by adding a value to the current program counter value stored in the program counter register using a standard add operation. 13. The processing core as recited in claim 10, wherein program jump tables hold values, which are offset values from the current program counter value. 14. The processing core as recited in claim 10, wherein a processing instruction comprises N-number of P-bit instructions appended together to form a very long instruction word (VLIW), and said N-number of processing paths process N-number of P-bit instructions in parallel. 15. The processor chip as recited in claim 14, wherein M=64, Q=64, and P=32. 16. The processing core as recited in claim 15, wherein Q=64, and a 64-bit special register stores bits indicating whether a register in a register file is a private register or a global register, each bit in the 64-bit special register corresponding to one of said registers in said register file. 17. The processing core of claim 10, wherein said one or more register files are included within said processing pipeline. 18. The a computer system, a scalable computer processing architecture, comprising: one or more processor chips, each comprising: a processing core, including: a processing pipeline having N-number of processing paths, each of said processing paths for processing instructions on M-bit data words; and one or more register files, each having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide, wherein one of the Q-number of general purpose registers comprises a program counter register that holds a current program counter value and the one or more register files may be accessed by at least two of said N-number of processing paths; an I/O link configured to communicate with other of said one or more processor chips or with I/O devices; a communication controller in electrical communication with said processing core and said I/O link; said communication controller for controlling the exchange of data between a first one of said one or more processor chips and said other of said one or more processor chips; wherein said processing core is fabricated on a single silicon die; and wherein said computer processing architecture can be scaled larger by connecting together two or more of said processor chips in parallel via said I/O links of said processor chips, so as to create multiple processing core pipelines which share data therebetween. 19. The computer processing architecture as recited in claim 18, wherein program jumps are executed by adding a value to the current program counter value stored in the program counter register using a standard add operation. 20. The processing core as recited in claim 18, wherein memory addresses are calculated by adding a value to the current program counter value stored in the program counter register using a standard add operation. 21. The computer processing architecture as recited in claim 18, wherein a processing instruction comprises N-number of P-bit instructions appended together to form a very long instruction word (VLIW) , and said N-number of processing paths process N-number of P-bit instructions in parallel. 22. The computer processing architecture as recited in claim 21, wherein M=64, Q=64, and P=32. 23. The computer processing architecture as recited in claim 18, wherein said Q-number of general purpose registers within each of said one or more register files are either private or global registers, and wherein when a value is written to one of said Q-number of said registers which is a global register within one of said plurality of register files, said value is propagated to a corresponding global register in the other of said one or more register files, and wherein when a value is written to one of said Q-number of said registers which is a private register within one of said one or more register files, said value is not propagated to a corresponding register in the other of said one or more register files. 24. The computer processing architecture as recited in claim 23, wherein Q=64, and a 64-bit special register stores bits indicating whether a register in a register file is a private register or a global register, each bit in the 64-bit special register corresponding to one of said registers in said register file. 25. The computer processing architecture as recited in claim 23, wherein said dedicated program counter register is a global register. 26. The scalable computer processing architecture of claim 18, wherein said one or more register files are included within said processing pipeline. 27. The a processing core comprising a processing pipeline having N-number of processing paths, each of said processing paths for processing instructions on M-bit data words, and one or more register files having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide, a method for jumping from one location in a program to another location in a program, comprising the steps of: storing a current program counter value in a dedicated program counter register, which is a first one of said Q-number of general purpose registers in at least one of said one or more register files; and adding a value to said current program counter value stored in said dedicated program counter register using a standard add operation, wherein a second one of said Q-number of general purpose registers in at least one of said one or more register files is hardwired to a set value; and wherein said processing core is fabricated on a single silicon die. 28. The processing core of claim 27, wherein said one or more register files are included within said processing pipeline. 29. The a processing core comprising a processing pipeline having N-number of processing paths, each of said processing paths for processing instructions on M-bit data words, and one or more register files having Q-number of general purpose registers, said Q-number of general purpose registers being M-bits wide, a method for calculating a memory address, comprising the steps of: storing a current program counter value in a dedicated program counter register which is a first one of said Q-number of general purpose registers in at least one of said one or more register files; and adding a value to said current program counter value stored in said program counter register using a standard add operation, wherein a second one of said Q-number of general purpose registers in said at least one of said one or more register files is hardwired to a set value; wherein said at least one of said one or more register files may be accessed by at least two of said N-number of processing paths; and wherein said processing core is fabricated on a single silicon die. 30. The processing core of claim 29, wherein said one or more register files are included within said processing pipeline.