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Method for programming programmable logic device having specialized functional blocks 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0463688 (2003-06-16)
발명자 / 주소
  • Tharmalingam,Kumara
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Fish &
인용정보 피인용 횟수 : 4  인용 특허 : 49

초록

A programming method efficiently programs programmable logic devices of the type having specialized functional blocks. Those blocks may include multipliers and other arithmetic function elements, or may be various types of memory blocks. In order to efficiently program devices having such specialize

대표청구항

What is claimed is: 1. For use with a programmable logic device including specialized functional blocks that perform specialized functions that also can be performed in other resources of the programmable logic device different from said specialized functional blocks, a method of programming such a

이 특허에 인용된 특허 (49)

  1. Pedersen Bruce, Apparatus and method for partitioning logic into a programmable logic device.
  2. Rajski Janusz ; Tyszer Jerzy,PLX, Arithmetic built-in self test of multiple scan-based integrated circuits.
  3. Jiang Shao-Kun ; Wong Roney S. ; Peter-Song Seungyoon, Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel.
  4. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  5. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  6. New Bernard J., Field programmable gate array with distributed gate-array functionality.
  7. New Bernard J., Field programmable gate array with mask programmable I/O drivers.
  8. New Bernard J., Field programmable gate array with mask programmable I/O drivers.
  9. Yano Naoka,JPX ; Tamura Naoyuki,JPX, High-efficiency multiplier and multiplying method.
  10. Krishna Rangasayee, Integrated circuit incorporating a programmable cross-bar switch.
  11. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  12. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  13. John Anthony Schadt, Integrated circuit with standard cell logic and spare gates.
  14. Sugimoto Tai (Columbia) Kobayashi Hideaki (Columbia SC) Shindo Masahiro (Osaka) Nakayama Haruo (Osaka JPX), Integrated silicon-software compiler.
  15. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
  16. Steele Randy C. (Southlake TX), Logic block for programmable logic devices.
  17. Beiu Valeriu, Logic gate having reduced power dissipation and method of operation thereof.
  18. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.
  19. New Bernard J. (Los Gatos CA), Logic structure and circuit for fast carry.
  20. Baeg Sanghyeon, Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment.
  21. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.
  22. Frederic Reblewski FR, Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system.
  23. De Vivek K. ; Ye Yibin, Method and apparatus for reducing standby leakage current using a transistor stack effect.
  24. Kojima Hirotsugu ; Shridhar Avadhani, Method and apparatus for reducing the power consumption in a programmable digital signal processor.
  25. Schultz David P. ; Young Steven P. ; Hung Lawrence C., Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA.
  26. Michael Timothy Moore, Method and system for proactively debugging fitting problems in programmable logic devices.
  27. Glenn A. Baxter, Method for converting programmable logic devices into standard cell devices.
  28. Baxter, Glenn A., Method for improving area in reduced programmable logic devices.
  29. L. James Hwang ; Cameron D. Patterson, Method for remapping logic modules to resources of a programmable gate array.
  30. Douglass, Stephen M., Method of designing integrated circuit having both configurable and fixed logic circuitry.
  31. Jenkins ; IV. Jesse H. ; Seltzer Jeffrey H. ; Curd Derek R., Method of minimizing power use in programmable logic devices.
  32. Telikepalli Anil L. N., Multiplier circuit design for a programmable logic device.
  33. New Bernard J., Multiplier fabric for use in field programmable gate arrays.
  34. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.
  35. Oswald William A. (Allentown PA) Singh Satwant (Macungie PA), Programmable function unit as parallel multiplier cell.
  36. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
  37. Rangasayee Krishna ; Bielby Robert N., Programmable logic device architecture incorporating a dedicated cross-bar switch.
  38. Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
  39. Lane Christopher F. ; Reddy Srinivas T. ; Cliff Richard G. ; Zaveri Ketan H. ; Pedersen Bruce B. ; Veenstra Kerry, Programmable logic device circuitry for improving multiplier speed and/or efficiency.
  40. Patel Rakesh H. (Santa Clara CA) Turner John E. (Santa Cruz CA) Wong Myron W. (San Jose CA), Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnec.
  41. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  42. Baxter, Glenn A., Programmable logic device structures in standard cell devices.
  43. Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
  44. Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA), Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers.
  45. Sharpe-Geisler Bradley A. ; Moyer Bryon I., Programmable logic device with multi-level power control.
  46. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.
  47. Steele Randy C. (Scottsdale AZ) Raad Safoin A. (Scottsdale AZ), Programmable summing functions for programmable logic devices.
  48. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
  49. Mori Shojiro (Kawasaki JPX), Transfer circuit for operation test of LSI systems.

이 특허를 인용한 특허 (4)

  1. Ozguz, Volkan H.; Carlson, Randolph S.; Gann, Keith D.; Leon, John; Boyd, W. Eric, Field programmable gate array utilizing dedicated memory stacks in a vertical layer format.
  2. Parry, Stuart; Stansfield, Anthony, Method of configuring embedded application-specific functional blocks.
  3. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.
  4. Carreira,Alexander; Vogenthaler,Alexander R., Visualizing hardware cost in high level modeling systems.
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