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Preparation of electroless deposition solutions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-018/31
  • B05D-001/18
출원번호 US-0609443 (2003-06-26)
발명자 / 주소
  • Choi,Hok Kin
  • Thirumala,Vani
  • Dubin,Valery
  • Cheng,Chin chang
  • Zhong,Ting
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 5  인용 특허 : 43

초록

A system and method for storing a solution containing a subset of a group consisting of a metal ion, a complexing agent, an ammonium salt, and a strong base and then nearer to a time of use in an electroless deposition process, using the solution to form an electroless deposition solution containing

대표청구항

What is claimed is: 1. A method comprising: storing for at least two days a solution containing a subset of a group consisting of a metal ion, a complexing agent, an ammonium salt, and a strong base, wherein the subset includes at least two components of the group; and nearer to a time of use in an

이 특허에 인용된 특허 (43)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
  2. Barth, Hans-Joachin; Kaltalioglu, Erdem, Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices.
  3. Kakizawa Masahiko,JPX ; Umekita Ken-ichi,JPX ; Hayashida Ichiro,JPX, Cleaning agent for a semi-conductor substrate.
  4. Hsiung Chiung-Sheng,TWX ; Hsieh Wen-Yi,TWX ; Lur Water,TWX, Copper damascene technology for ultra large scale integration circuits.
  5. James A. Cunningham, Diffusion barriers for copper interconnect systems.
  6. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  7. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  8. Shacham-Diamand Yosi ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless deposition equipment or apparatus and method of performing electroless deposition.
  9. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  10. LeBlanc ; Jr. Oliver H. (Schenectady NY), Electroless nickel plating composition and method for its preparation and use.
  11. Kumasaka Osamu (Yamanashi JPX) Yamaoka Nobuki (Yamanashi JPX), Electroless plating method and apparatus.
  12. Ting Chiu H. (Saratoga CA) Pai Pei-Lin (Cupertino CA), Fully planar metalization process.
  13. Mehta Sunil (San Jose CA), High density multi-level metallization and interconnection structure.
  14. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  15. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  16. DeLuca Michael A. (Holbrook NY) McCormack John F. (Roslyn Heights NY), Metallization of ceramics.
  17. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  18. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  19. John O. Dukovic ; William E. Corbin, Jr. ; Erick G. Walton ; Peter S. Locke ; Panayotis C. Andricacos ; James E. Fluegel ; Evan Patton ; Jonathan Reid, Method of controlling chemical bath composition in a manufacturing environment.
  20. Steven C. Avanzino ; Kai Yang ; Sergey Lopatin ; Todd P. Lukanc, Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film.
  21. Hsu Shih-Ying,TWX, Method of fabricating metal interconnect.
  22. Brain Ruth A., Method of forming a metal line utilizing electroplating.
  23. Orita, Toshiyuki, Method of forming a via hole in a semiconductor device.
  24. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  25. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  26. Leu, Jihperng; Thomas, Christopher D., Method of making semiconductor device using an interconnect.
  27. Ning, Xian J., Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation.
  28. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
  29. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  30. Miller Richard G. (Pittsburgh PA) Cavitt Roy L. (New Kensington PA), Novel method for the rapid deposition of gold films onto non-metallic substrates at ambient temperatures.
  31. Zeblisky Rudolph J. (Hauppauge NY), Novel precious metal sensitizing solutions.
  32. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  33. Hussein Makarem A., Process to manufacture continuous metal interconnects.
  34. Paunovic Milan ; Jahnes Christopher, Production of electroless Co(P) with designed coercivity.
  35. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  36. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  37. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  38. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  39. Nogami, Takeshi; Komai, Naoki; Kito, Hideyuki; Taguchi, Mitsuru, Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof.
  40. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  41. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.
  42. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  43. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (5)

  1. De Rege Thesauro,Francesco; Brusic,Vlasta; Bayer,Benjamin P., Chemical-mechanical polishing of metals in an oxidized form.
  2. Defalco, Frank G., Compositions and processes for deposition of metal ions onto surfaces of conductive substrates.
  3. Kolics, Artur; Li, Nanhai, Processes and solutions for substrate cleaning and electroless deposition.
  4. Christenson,Kurt Karl, Reagent activator for electroless plating.
  5. Kolics, Artur, Solutions and methods for metal deposition.
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