초록 ▼

Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon l

Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.

대표청구항 ▼

What is claimed is: 1. A method comprising: forming a layer of variable density porous silicon on a top surface of a silicon substrate; depositing a layer of silicon on the layer of variable density porous silicon; forming a device layer of an integrated circuit device within the layer of silicon;

What is claimed is: 1. A method comprising: forming a layer of variable density porous silicon on a top surface of a silicon substrate; depositing a layer of silicon on the layer of variable density porous silicon; forming a device layer of an integrated circuit device within the layer of silicon; bonding a temporary support layer to the device layer; splitting the variable density porous silicon layer; removing any portion of the variable density porous silicon layer from the silicon layer; and removing the temporary support layer from the device layer. 2. The method of claim 1 further comprising: packaging the device layer using standard integrated circuit packaging; and bonding the thin device layer to an integrated heat spreader. 3. The method of claim 1 wherein the silicon layer is approximately 10-50 microns thick and the device layer is approximately 0. 1-1 micron thick. 4. The method of claim 1 wherein the layer of variable density porous silicon is formed using an anodization process. 5. The method of claim 1 wherein the support layer is bonded to the device layer using adhesive. 6. The method of claim 1 wherein the support layer is plastic. 7. The method of claim 1 wherein polishing is used to remove any portion of the variable density porous silicon layer from the silicon layer.