IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0163492
(2002-06-07)
|
우선권정보 |
JP-2001-234263(2001-08-01) |
발명자
/ 주소 |
- Suminoe,Shinji
- Nakanishi,Hiroyuki
- Ishio,Toshiya
- Iwazaki,Yoshihide
- Mori,Katsunobu
|
출원인 / 주소 |
|
대리인 / 주소 |
Birch, Stewart, Kolasch &
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인용정보 |
피인용 횟수 :
25 인용 특허 :
22 |
초록
▼
A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to
A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.
대표청구항
▼
What is claimed is: 1. A semiconductor device, comprising: a semiconductor substrate; an electrode pad formed on said semiconductor substrate; a first insulation layer formed on said semiconductor substrate except for the area having the electrode pad; an external connecting terminal; a leading wi
What is claimed is: 1. A semiconductor device, comprising: a semiconductor substrate; an electrode pad formed on said semiconductor substrate; a first insulation layer formed on said semiconductor substrate except for the area having the electrode pad; an external connecting terminal; a leading wiring layer connecting said external connecting terminal to said electrode pad and formed on a surface, opposite to the semiconductor substrate, of said first insulation layer, said leading wiring layer including a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer, and the first barrier metal layer and the second barrier metal layer cover entire surroundings including the side, bottom and top surfaces of the main conductor layer, and the main conductor layer including a base layer and a main layer, which is formed by plating; a second insulation layer, formed on said first insulation layer, covering side surfaces of the leading wiring layer substantially to the top surface of the main conductor layer; and a third insulation layer formed on said second insulation layer and said leading wiring layer. 2. The semiconductor device as set forth in claim 1, further comprising: a metal layer made of gold or platinum group formed at least in a connecting section of the second barrier metal layer and the external connecting terminal. 3. The semiconductor device as set forth in claim 2, wherein: the first barrier metal layer is made of alloy of tungsten and titanium. 4. The semiconductor device as set forth in claim 3, wherein: the main conductor layer is made of copper, and the second barrier metal layer is made of nickel. 5. The semiconductor device as set forth in claim 1, wherein: the first barrier metal layer is made of alloy of tungsten and titanium. 6. The semiconductor device as set forth in claim 1, wherein: the main conductor layer is made of copper, and the second barrier metal layer is made of nickel. 7. The semiconductor device as set forth in claim 1, wherein said first insulation layer includes an inorganic insulation film formed on the surface of said semiconductor substrate and an organic insulation layer formed on said inorganic insulation film. 8. The semiconductor device as set forth in claim 7, wherein said inorganic insulation film is made of a nitride. 9. A semiconductor device, comprising: a semiconductor substrate; an electrode pad formed on said semiconductor substrate; a first insulation layer formed on said semiconductor substrate except for the area having the electrode pad; an external connecting terminal; a leading wiring layer connecting said external connecting terminal to said electrode pad and formed on a surface, opposite to the semiconductor substrate, of said first insulation layer, said leading wiring layer including a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer, and the first barrier metal layer and the second barrier metal layer cover entire surroundings including the side, bottom and top surfaces of the main conductor layer; a second insulation layer, formed on the first insulation layer, for covering side surfaces of the leading wiring layer; and a third insulation layer formed on the second insulation layer and on the leading wiring layer without contacting the side surfaces of the first barrier metal layer. 10. The semiconductor device as set forth in claim 9, further comprising: a metal layer made of gold or platinum group formed at least in a connecting section of the second barrier metal layer and the external connecting terminal. 11. The semiconductor device as set forth in claim 10, wherein: the first barrier metal layer is made of alloy of tungsten and titanium. 12. The semiconductor device as set forth in claim 11, wherein: the main conductor layer is made of copper, and the second barrier metal layer is made of nickel. 13. The semiconductor device as set forth in claim 9, wherein: the first barrier metal layer is made of alloy of tungsten and titanium. 14. The semiconductor device as set forth in claim 9, wherein: the main conductor layer is made of copper, and the second barrier metal layer is made of nickel. 15. The semiconductor device as set forth in claim 9, wherein said first insulation layer includes an inorganic insulation film formed on the surface of said semiconductor substrate and an organic insulation layer formed on said inorganic insulation film. 16. The semiconductor device as set forth in claim 15, wherein said inorganic insulation film is made of a nitride.
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