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Semiconductor device having a leading wiring layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0163492 (2002-06-07)
우선권정보 JP-2001-234263(2001-08-01)
발명자 / 주소
  • Suminoe,Shinji
  • Nakanishi,Hiroyuki
  • Ishio,Toshiya
  • Iwazaki,Yoshihide
  • Mori,Katsunobu
출원인 / 주소
  • Sharp Kabushiki Kaisha
대리인 / 주소
    Birch, Stewart, Kolasch &
인용정보 피인용 횟수 : 25  인용 특허 : 22

초록

A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to

대표청구항

What is claimed is: 1. A semiconductor device, comprising: a semiconductor substrate; an electrode pad formed on said semiconductor substrate; a first insulation layer formed on said semiconductor substrate except for the area having the electrode pad; an external connecting terminal; a leading wi

이 특허에 인용된 특허 (22)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Erdos George (Toronto CAX), Bump structure for bonding to a semi-conductor device.
  3. Jamin Ling ; Dave Charles Stepniak, Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor.
  4. Okada Takashi,JPX ; Hirano Naohiko,JPX ; Tazawa Hiroshi,JPX ; Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Doi Kazuhide,JPX ; Hiruta Yoichi,JPX ; Shibasaki Koji,JPX, Flip-chip connection type semiconductor integrated circuit device.
  5. Farnworth Warren M., Mask repattern process.
  6. Cunningham, James A., Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby.
  7. Chan Seung Hwang KR; Seung Ouk Jung KR, Method for manufacturing semiconductor devices having redistribution patterns with a concave pattern in a bump pad area.
  8. Jang Syun-Ming,TWX, Method of enclosing copper conductor in a dual damascene process.
  9. Yeung Ming Chow HK; Zaheed Sadrudin Karim HK, Method of fabrication of barrier cap for under bump metal.
  10. Maitani, Touta; Nishihara, Shinji, Method of forming bump electrodes.
  11. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
  12. Shinogi, Hiroyuki; Tokushige, Ryoji; Takai, Nobuyuki, Method of manufacturing a chip size package.
  13. Hatcher ; Jr. Owen W. (Sunnyvale CA), Method of performing electrical reject selection.
  14. Krishnan Ajay (11411 Research Blvd. #1123 Austin TX 78759) Kumar Nalin (12116 Scribe Dr. Austin TX 78727), Multilevel metallization process using polishing.
  15. Hirano, Takashi; Yamamoto, Kagehisa; Banba, Toshio; Makabe, Hiroaki, Semiconductor device.
  16. Hayashi Jun (Tokyo JPX) Yamanaka Michiko (Tokyo JPX), Semiconductor device and fabrication process therefor.
  17. Fujisawa, Kazunori; Awaya, Nobuyoshi, Semiconductor device and its production process.
  18. Hiroyuki Shinogi JP; Nobuyuki Takai JP; Ryoji Tokushige JP, Semiconductor device and method of manufacturing the same.
  19. Mori Katsunobu (Nara JPX), Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film.
  20. Tomoyuki Fukuda JP; Eiji Watanabe JP, Semiconductor device with bumps for pads.
  21. Watanabe Eiji,JPX ; Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Nagashige Kenichi,JPX ; Onodera Masanori,JPX ; Kodama Kunio,JPX ; Yoda Hiroyuki,JPX ; Fujimori Joji,JPX ; Nakada Minoru,JPX ; Makino Yuta, Semiconductor device with flip chip bonding pads and manufacture thereof.
  22. Narizuka, Yasumori; Itou, Mitsuko; Yamaguchi, Yoshihide; Tenmei, Hiroyuki, Wiring board and its production method, semiconductor device and its production method, and electronic apparatus.

이 특허를 인용한 특허 (25)

  1. Ho,Kwun Yao; Kung,Moriss; Chang,Wen Yuan; Lu,Hsueh Chung Shelton, Chip and manufacturing method and application thereof.
  2. Shih, Chien Hsueh; Tsai, Minghsing; Su, Hung Wen; Shue, Shau Lin, Copper interconnection with conductive polymer layer and method of forming the same.
  3. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  4. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  5. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  6. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  7. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  8. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  9. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  10. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  11. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  12. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  13. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  14. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  15. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  16. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  17. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  18. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  19. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  20. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  21. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  22. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  23. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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