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Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detecti

Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence. An initial value controller provides the registers with a selected one of two initial values separately determined for the two data sequences.

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What is claimed is: 1. An apparatus for generating an error detection information sequence for determining a length of data sequence transmitted, in a communication system which can transmit at least two data sequences with different lengths through a data channel, and transmit through a data contr

What is claimed is: 1. An apparatus for generating an error detection information sequence for determining a length of data sequence transmitted, in a communication system which can transmit at least two data sequences with different lengths through a data channel, and transmit through a data control channel a control data sequence for each of the at least two data sequences, each of the control data sequences having a same length as the at least two data sequences, respectively, and including a control information sequence indicating information with regard to each of the at least two data sequences and an error detection information sequence for detecting an error of the control information sequence, the apparatus comprising: a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence; a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the addition result through an output path; an operator that, during reception of the control information sequence, generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register among the registers and provides the generated feedback bit sequence to the adders, and after completion of receiving the control information sequence, sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information sequence; and an initial value controller for providing the registers with a selected one of two initial values separately determined for the two data sequences. 2. The apparatus of claim 1, wherein the operator comprises: a first switch for selectively outputting the control information sequence and the preset input bit; an output adder for adding an output of the first switch to output bits of the final register; a second switch for selectively providing an output of the output adder and the preset input bit as the feedback bit sequence to the adders; and a third switch for selectively outputting the control information sequence and the error detection information bit sequence from the output adder. 3. The apparatus of claim 2, wherein the first switch outputs the control information sequence during reception of the control information sequence, and outputs the preset input bit after completion of receiving the control information sequence. 4. The apparatus of claim 3, wherein the second switch provides an output of the output adder to the adders during reception of the control information sequence, and provides the preset input bit to the adders after completion of receiving the control information sequence. 5. The apparatus of claim 4, wherein the third switch outputs the control information sequence during reception of the control information sequence, and outputs the error detection information sequence after completion of receiving the control information sequence. 6. The apparatus of claim 1, wherein the at least two data sequences have different slot lengths. 7. The apparatus of claim 6, wherein one data sequence among the at least two data sequences is two times longer in slot length than the other data sequence. 8. An apparatus for generating a transmission information sequence by attaching an error detection information bit sequence to an input information sequence of a first information sequence or a second information sequence, in a communication system which encodes a first information sequence with a first length at a predetermined coding rate before transmission, and encodes a second information sequence with a second length being F times (where, F is a multiple of 2) the first length at the predetermined coding rate before F-time repeated transmission, the apparatus comprising: a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence; a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the addition result through an output path; an operator that, during reception of the input information sequence, generates the feedback bit sequence by sequentially adding bits of the input information sequence to output bits of a final register among the registers, provides the generated feedback bit sequence to the adders, and outputs the input information sequence as the transmission information sequence, and after completion of receiving the input information sequence, provides a preset input bit to the adders, sequentially adds the preset input bit to output bits of the final register to generate an error detection information bit sequence, and outputs the error detection information bit sequence as the transmission information sequence; and an initial value controller for providing the registers with a selected one of two initial values separately determined for the first information sequence and the second information sequence, wherein the input information sequence is a control information sequence of a packet data sequence, and the control information sequence and the packet data sequence have a same length. 9. The apparatus of claim 8, wherein the first information sequence is a control information sequence with a 2-slot length; and the second information sequence is a control information sequence with a 4-slot length. 10. The apparatus of claim 8, wherein the operator comprises: a first switch for selectively outputting the input information sequence and the preset input bit; an output adder for adding an output of the first switch to output bits of the final register; a second switch for selectively providing the adders with an output of the output adder and the preset input bit as the feedback bit sequence; and a third switch for selectively outputting the input information sequence and the output bits of the output adder as the transmission information sequence. 11. An apparatus for checking an error of a received control data sequence to detect a length of data sequences transmitted over a data channel, in a communication system including a transmitter which can transmit at least two data sequences with different lengths through the data channel and transmit through a data control channel a control data sequence for each of the at least two data sequences, each of the control data sequences having a same length as the at least two data sequences, respectively, and having a control information sequence indicating information with regard to each data sequence and an error detection information sequence for detecting an error in the control information sequence, and a receiver which receives data sequences transmitted over the data channel from the transmitter and a control data sequence transmitted over the data control channel from the transmitter, the apparatus comprising: a plurality of cascaded registers, a the number of the registers being equivalent to a number of bits in the error detection information sequence; a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the addition result through an output path; an operator that, during reception of the control information sequence, generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register among the registers and provides the generated feedback bit sequence to the adders, and after completion of receiving the control information sequence, sequentially adds a preset input bit to output bits of the final register and outputs the addition result as a received error detection information sequence; an initial value controller for providing the registers with a selected one of at least two initial values separately determined for the at least two data sequences; and an error decision block for comparing the received error detection information bit sequence with an error detection information bit sequence corresponding to the selected initial value, thus to determine existence of an error. 12. The apparatus of claim 11, wherein the operator comprises: a first switch for selectively outputting the control information sequence and the preset input bit; an output adder for adding an output of the first switch to output bits of the final register; a second switch for selectively providing the adders with an output of the output adder and the preset input bit as the feedback bit sequence; and a third switch for selectively outputting the received control information sequence and the received error detection information bit sequence from the output adder. 13. The apparatus of claim 11, wherein one data sequence among the at least two data sequences is two times longer in slot length than another data sequence. 14. The apparatus of claim 11, wherein the preset input bit has a value of "0." 15. An apparatus for checking an error of a received information sequence in a communication system including a transmitter which encodes a first information sequence with a first length at a predetermined coding rate before transmission, and encodes a second information sequence with a second length being F times (where, F is a multiple of 2) the first length at the predetermined coding rate before F-time repeated transmission, and attaches an error detection information sequence to the first information sequence or the second information sequence and transmits the result as a transmission information sequence, and a receiver which receives an information sequence from the transmitter, the apparatus comprising: a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence; a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the result through an output path; an operator that, during reception of the received information sequence, generates the feedback bit sequence by sequentially adding bits of the received information sequence to output bits of a final register among the registers, and provides the generated feedback bit sequence to the adders, and after completion of receiving the received information sequence, provides a preset input bit to the adders, sequentially adds the preset input bit to output bits of the final register and outputs the addition result as a received error detection information sequence; an initial value controller for providing the registers with a selected one of two initial values separately determined for the first information sequence and the second information sequence; and an error decision block for comparing the received error detection information sequence with an error detection information sequence corresponding to the selected initial value, to determine existence of an error, wherein the first information sequence is a control information sequence of a first packet data sequence, the second information sequence is a control information sequence of a second packet data sequence, the first control information sequence and the first packet data sequence have a same length, and the second control information sequence and the second packet data sequence have a same length. 16. The apparatus of claim 15, wherein the first information sequence has a 2-slot length; and the second information sequence has a 4-slot length. 17. A method for generating an error detection information sequence for determining whether at least two data sequences are transmitted in different lengths, in a communication system which can transmit the at least two data sequences with different lengths through a data channel, and transmit through a data control channel a control data sequence for each of the at least two data sequences, each of the control data sequences having a same length as the at least two data sequences, respectively, and including a control information sequence indicating information with regard to each data sequence and an error detection information sequence for detecting an error of the control information sequence, the method comprising the steps of: providing a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information bit sequence, and a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the addition result through an output path; providing the registers with a selected one of at least two initial values separately determined for the at least two data sequences; during reception of the control information sequence, generating the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register among the registers and providing the generated feedback bit sequence to the adders; after completion of receiving the control information sequence, sequentially adding a preset input bit to output bits of the final register and outputting the addition result as the error detection information bit sequence. 18. The method of claim 17, wherein one data sequence among the at least two data sequences is two times longer in slot length than another data sequence. 19. The method of claim 17, wherein the preset input bit has a value of "0." 20. A method for generating a transmission information sequence by attaching an error detection information sequence to an input information sequence of a first information sequence or a second information sequence, in a communication system which encodes a first information sequence with a first length at a predetermined coding rate before transmission, and encodes a second information sequence with a second length being F times (where, F is a multiple of 2) the first length at the predetermined coding rate before F-time repeated transmission, the method comprising the steps of: providing a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence, and a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the result through an output path; providing the registers with a selected one of two initial values separately determined for the first information sequence and the second information sequence; during reception of the input information sequence, generating the feedback bit sequence by sequentially adding bits of the input information sequence to output bits of a final register among the registers, providing the generated feedback bit sequence to the adders, and outputting the input information sequence as the transmission information sequence; and after completion of receiving the input information sequence, providing a preset input bit to the adders, sequentially adding the preset input bit to output bits of the final register to generate an error detection information sequence, and outputting the error detection information bit sequence as the transmission information sequence, wherein the input information sequence is a control information sequence of a packet data sequence, and the control information sequence and the packet data sequence have a same length. 21. The method of claim 20, wherein the first information sequence is a control information sequence with a 2-slot length, and the second information sequence is a control information sequence with a 4-slot length. 22. The method of claim 20, wherein the preset input bit has a value of "0." 23. A method for checking an error of a received control data sequence to detect a length of data sequences transmitted over a data channel, in a communication system including a transmitter which can transmit at least two data sequences with different lengths through the data channel and transmit through a data control channel a control data sequence for each of the at least two data sequences, the control channel sequences having a same length as the at least two data sequences, respectively, and having a control information sequence indicating a data rate and a data transmission format of each data sequence and an error detection information sequence for detecting an error in the control information sequence, and a receiver which receives data sequences transmitted over the data channel from the transmitter and a control data sequence transmitted over the data control channel from the transmitter, the method comprising the steps of: providing a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence, and a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the result through an output path; providing the registers with a selected one of two initial values separately determined for the two data sequences; during reception of the control information sequence included in the received control data sequence, generating the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register among the registers and providing the generated feedback bit sequence to the adders; after completion of receiving the control information sequence, sequentially adding a preset input bit to output bits of the final register and outputting the addition result as a received error detection information sequence; and comparing the received error detection information sequence with an error detection information sequence corresponding to the selected initial value, thus to determine existence of an error. 24. The method of claim 23, wherein one data sequence among the at least two data sequences is two times longer in slot length than another data sequence. 25. The method of claim 23, wherein the preset input bit has a value of "0." 26. A method for checking an error of a received information sequence in a communication system including a transmitter which encodes a first information sequence with a first length at a predetermined coding rate before transmission, and encodes a second information sequence with a second length being F times (where, F is a multiple of 2) the first length at the predetermined coding rate before F-time repeated transmission, and attaches an error detection information sequence to the first information sequence or the second information sequence and transmits the result as a transmission information sequence, and a receiver which receives an information sequence from the transmitter, the method comprising the steps of: providing a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence, and a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the result through an output path; providing the registers with a selected one of two initial values separately determined for the first information sequence and the second information sequence; during reception of the received information sequence, generating the feedback bit sequence by sequentially adding bits of the received information sequence to output bits of a final register among the registers, and providing the generated feedback bit sequence to the adders; after completion of receiving the received information sequence, providing a preset input bit to the adders, sequentially adding the preset input bit to output bits of the final register and outputting the addition result as a received error detection information sequence; and comparing the received error detection information sequence with an error detection information sequence corresponding to the selected initial value, thus to determine existence of an error, wherein the first information sequence is a control information sequence of a first packet data sequence, the second information sequence is a control information sequence of a second packet data sequence, the first control information sequence and the first packet data sequence have a same length, and the second control information sequence and the second packet data sequence have a same length. 27. The method of claim 26, wherein the first information sequence has a 2-slot length, and the second information sequence has a 4-slot length. 28. The method of claim 26, wherein the preset input bit has a value of "0." 29. An apparatus for generating an error detection information sequence for determining a length of data sequence transmitted, in a communication system which can transmit at least two data sequences with different lengths through a data channel, and transmit through a data control channel a control data sequence, the control data sequence including a control information sequence indicating information with regard to each of the at least two data sequences and an error detection information sequence for detecting an error of the control information sequence, the apparatus comprising: a plurality of cascaded registers, the number of the registers being equivalent to the number of bits in the error detection information sequence; a plurality of adders determined by a predetermined generator polynomial positioned between the registers, each of the adders adding a bit sequence received through an input path to a feedback bit sequence and outputting the addition result through an output path; an operator that, during reception of the control information sequence, generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register among the registers and provides the generated feedback bit sequence to the adders, and after completion of receiving the control information sequence, sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information sequence; and an initial value controller for separately determining a unique initial value for each different length data sequence, and providing the registers with a selected one of the at least two initial values separately determined for the at least two data sequences.