[특허]Apparatus for deforming resilient contact structures on semiconductor components

[미국특허] Apparatus for deforming resilient contact structures on semiconductor components 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	B21F-001/02 B21F-001/00
출원번호	US-0893685 (2004-07-16)
발명자 / 주소	Cram,Daniel P.
출원인 / 주소	Micron Technology, Inc.
인용정보	피인용 횟수 : 4 인용 특허 : 37

초록 ▼

A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resilient contact structures are used to test the components to identify functional and non-functional components. Following this test, the resilient contact structures on the non-functional components are deformed, such that electrical communication with the non-functional components is prevented in a subsequent burn-in test. This permits the burn-in test to be performed using "shared resources" test equipment. A deformation apparatus for deforming the resilient contact structures includes a deformation block configured to compress, bend or shape the resilient contact structures on the non-functional dice.

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I claim: 1. A method for planarizing resilient contact structures on a semiconductor component comprising: providing a deformation apparatus configured to physically engage the resilient contact structures; physically engaging the resilient contact structures using the deformation apparatus; and following the physically engaging step, moving the deformation apparatus or the component, or both the deformation apparatus and the component, in X, Y and Z directions to bend, compress or shape the resilient contact structures. 2. The method of claim 1 wherein the deformation apparatus is configured to electrically engage the resilient contact structures for transmitting test signals to the component. 3. The method of claim 1 wherein the deformation apparatus comprises a deformation block comprising a plurality of retention structures configured to retain the resilient contact structures during the moving step. 4. The method of claim 1 wherein the deformation apparatus comprises a deformation block comprising a plurality of retention structures comprising pockets, grooves or a rough surface. 5. An apparatus for deforming resilient contact structures on a semiconductor component contained on a substrate comprising: a deformation block comprising a plurality of retention structures configured to compress, bend or shape the resilient contact structures; a first holder configured to hold and move the deformation block to compress, bend or shape the resilient contact structures; and a second holder configured to hold the substrate proximate to the deformation block, the first holder, the second holder, or both the first holder and the second holder, movable in X, Y and Z directions. 6. The apparatus of claim 5 wherein the deformation block further comprises a plurality of retention structures configured to retain the resilient contact structures during compression, bending or shaping thereof. 7. The apparatus of claim 5 wherein the deformation apparatus further comprises a plurality of retention structures configured to electrically engage the resilient contact structures and to transmit test signals thereto. 8. An apparatus for deforming resilient contact structures on a semiconductor component contained on a substrate comprising: a deformation block comprising a plurality of retention structures configured to compress, bend or shape the resilient contact structures; a first holder configured to hold and move the deformation block to compress, bend or shape the resilient contact structures; and a second holder configured to hold the substrate proximate to the deformation block, wherein the substrate comprises a semiconductor wafer and the component comprises a semiconductor die. 9. An apparatus for deforming resilient contact structures on a semiconductor component contained on a substrate comprising: a deformation block comprising a plurality of retention structures configured to compress, bend or shape the resilient contact structures; a first holder movable in X, Y and Z directions configured to hold and move the deformation block to compress, bend or shape the resilient contact structures; and a second holder configured to hold the substrate proximate to the deformation block. 10. An apparatus for deforming resilient contact structures on a semiconductor component contained on a substrate comprising: a deformation block comprising a plurality of retention structures configured to compress, bend or shape the resilient contact structures; a first holder configured to hold and move the deformation block to compress, bend or shape the resilient contact structures; and a second holder movable in X, Y and Z directions configured to hold the substrate proximate to the deformation block. 11. The apparatus of claim 10 wherein the retention structures are configured to planarize the resilient contact structures. 12. An apparatus for deforming resilient contact structures on a semiconductor die on a wafer comprising: a deformation block comprising a plurality of retention structures configured to physically engage and retain the resilient contact structures; a first holder configured to hold the deformation block; and a second holder configured to hold the wafer proximate to the deformation block; with either the first holder, the second holder, or both, movable in X, Y and Z directions such that the deformation block can compress, bend or shape the resilient contact structures. 13. The apparatus of claim 12 wherein the retention structures comprise openings in the deformation block. 14. The apparatus of claim 12 wherein the retention structures comprise a rough surface on the deformation block. 15. The apparatus of claim 12 further comprising a controller configured to control movement of the first holder or the second holder. 16. The apparatus of claim 12 wherein the retention structures comprise contact structures configured to electrically engage the resilient contact structures.

이 특허에 인용된 특허 (37) 인용/피인용 타임라인 분석

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Lorenzini Gianni (1049 Oregon Ave. Palo Alto CA 94303), Apparatus and method for straightening semi-conductor pins.
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Farnworth Warren ; Wood Alan, Apparatus for manufacturing known good semiconductor dice.
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Agahdel Fariborz ; Griswold Brad ; Husain Syed ; Moti Robert ; Robinette ; Jr. William C. ; Ho Chung W., Bare die carrier.
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Tuckerman David (Dublin CA) Patel Pradip (Redwood City CA), Burn-in technologies for unpackaged integrated circuits.
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Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.
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Krug Heinz (c/o Akademie Meru ; Station 24 NL-6063 Vlodrop NLX), Circuit arrangement for testing integrated circuit components.
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Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Component for connecting a semiconductor chip to a substrate.
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McClure David C. (Carrollton TX), Entire wafer stress test method for integrated memory devices and circuit therefor.
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Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
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Meuschke Robert E. (Penn Hills PA) Shields Edward P. (N. Huntingdon PA), Fuel assembly alignment pin straightening device.
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Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX), Full wafer integrated circuit testing device.
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Kjarsgaard Torben (15045 Saticoy ; No. 138 Van Nuys CA 91407), Lead straightening, aligning, and spacing implement for an electronic semi-conductor package.
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Foster James E. (Endwell NY), Method and apparatus for straightening and aligning leads and testing electrical functioning of components.
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Wood Alan G. ; Farnworth Warren M. ; Akram Salman ; Hembree David R., Method and apparatus for testing unpackaged semiconductor dice.
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Cram, Daniel P., Method and system for wafer level testing and burning-in semiconductor components.
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Cram, Daniel P., Method and system for wafer level testing and burning-in semiconductor components.
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Daniel P. Cram, Method and system for wafer level testing and burning-in semiconductor components.
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Hembree David R., Method for aligning and connecting semiconductor components to substrates.
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Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
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DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX), Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located.
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Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.
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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of mounting resilient contact structures to semiconductor devices.
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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
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Whetsel Lee D., Process of testing integrated circuit dies on a wafer.
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Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate.
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James Marc Leas ; Robert William Koss ; Jody John Van Horn ; George Frederick Walker ; Charles Hampton Perry ; David Lewis Gardell ; Steve Leo Dingle ; Ronald Prilik, Semiconductor wafer test and burn-in.
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Chio Chuy-Nan (Fl. 9-3 ; No. 333 ; Fu-Hsing N. Rd. Taipei City TWX), Socket for testing a plug-in type semiconductor.
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Beffa Ray ; Nevill Leland R. ; Farnworth Warren M. ; Cloud Eugene H. ; Waller William K., System for stressing a memory integrated circuit die.
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Pfaff Wayne K. (309 Steeplechase Irving TX 75062), Test socket for electronic device packages.
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Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.
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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Wafer-level test and burn-in, and semiconductor process.
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Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Wafer-scale techniques for fabrication of semiconductor chip assemblies.
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[미국특허] Apparatus for deforming resilient contact structures on semiconductor components 원문보기

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