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[미국특허] Method for fabricating wiring board provided with passive element 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/36
출원번호 US-0023499 (2004-12-29)
우선권정보 JP-P2001-170019(2001-06-05); JP-P2001-170020(2001-06-05)
발명자 / 주소
  • Fukuoka,Yoshitaka
  • Serizawa,Tooru
  • Yagi,Hiroshi
  • Shimada,Osamu
  • Hirai,Hiroyuki
  • Yamaguchi,Yuji
출원인 / 주소
  • Dai Nippon Printing Co., Ltd.
  • D.T. Circuit Technology Co., Ltd.
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett &
인용정보 피인용 횟수 : 12  인용 특허 : 22

초록

A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a

대표청구항

What is claimed is: 1. A method for fabricating a wiring board provided with a passive element, comprising: coating a resistive paste and/or a dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has the first surface and a second surfac

이 특허에 인용된 특허 (22) 인용/피인용 타임라인 분석

  1. Tserng Hua Quen ; Saunier Paul ; Sanzgiri Shashikant M., Antenna having elements with improved thermal impedance.
  2. Nomura Kazuo,JPX ; Nakanuma Nobutsugu,JPX ; Ishiyama Ichiro,JPX ; Higashi Koji,JPX ; Kato Masaki,JPX ; Nagare Ichiro,JPX ; Kurokawa Hiroyuki,JPX ; Ohara Yozo,JPX, Capacitor-mounted circuit board.
  3. Dunn Gregory J. ; Lach Larry ; Savic Jovica ; Beuhler Allyson ; Simons Everett, Circuit board features with reduced parasitic capacitance and method therefor.
  4. Odaira Hiroshi (Chigasaki JPX) Imamura Eiji (Yokosuka JPX) Wada Yusuke (Tokyo JPX) Arai Yasushi (Fujisawa JPX) Sasaoka Kenji (Zama JPX) Mori Takahiro (Yokohama JPX) Ikegaya Fumitoshi (Zama JPX) Kowat, Circuit devices and fabrication method of the same.
  5. Nakatani, Seiichi; Sugaya, Yasuhiro; Asahi, Toshiyuki; Komatsu, Shingo, Component built-in module and method for producing the same.
  6. Nakatani, Seiichi; Sugaya, Yasuhiro; Asahi, Toshiyuki; Komatsu, Shingo, Component built-in module and method for producing the same.
  7. Toshiyuki Asahi JP; Yasuhiro Sugaya JP; Shingo Komatsu JP; Seiichi Nakatani JP, Component built-in module and method of manufacturing the same.
  8. Hayama Masaaki,JPX ; Mohri Noboru,JPX ; Nakao Keiichi,JPX, Electronic part fabricated by intaglio printing.
  9. Tserng Hua Q. (Dallas TX) Saunier Paul (Garland TX), Integrated circuit with improved thermal impedance.
  10. Pfeifer Michael J. (Chandler AZ) Marlin George W. (Phoenix AZ), Method of fabricating a flip chip semiconductor device having an inductor.
  11. Bowles, Philip Harbaugh; Mobley, Washington Morris; Parker, Richard Dixon; Ellis, Marion Edmond, Method of forming integral passive electrical components on organic circuit board substrates.
  12. Klaser John J. (Springfield MO), Method of making a multilayer printed circuit board having screened-on resistors.
  13. Felten John James, Method to embed passive components.
  14. Nakatani, Seiichi; Bessho, Yoshihiro; Sugaya, Yasuhiro; Onishi, Keiji, Module with built-in electronic elements and method of manufacture thereof.
  15. Orihara Katsuhisa,JPX ; Fujimoto Masahiro,JPX ; Monkawa Haruo,JPX ; Kurita Hideyuki,JPX, Non-contact IC card and process for its production.
  16. Masatoshi Akagawa JP, Non-contact type IC card and process for manufacturing same.
  17. Powell, Douglas O., Organic dielectric electronic interconnect structures and method for making.
  18. Henderson James M. (Scottsdale AZ) Gibbs Terry L. (Tempe AZ), Printed circuit resistive element.
  19. Kakuhashi Takeshi (Ibaraki JPX) Miyake Yasufumi (Ibaraki JPX), Printed circuit substrate with resistance elements.
  20. Yamamoto Yuichi,JPX ; Sato Yoshizumi,JPX ; Motomura Tomohisa,JPX ; Hamano Hiroshi,JPX ; Arai Yasushi,JPX, Printed wiring board having an interconnection penetrating an insulating layer.
  21. Yamaguchi, Yoshihide; Terabayashi, Takao; Tenmei, Hiroyuki; Hozoji, Hiroshi; Kanda, Naoya, Semiconductor module and method of making the device.
  22. Fukuoka, Yoshitaka; Serizawa, Tooru; Yagi, Hiroshi; Shimada, Osamu; Hirai, Hiroyuki; Yamaguchi, Yuji, Wiring board provided with passive element and cone shaped bumps.

이 특허를 인용한 특허 (12) 인용/피인용 타임라인 분석

  1. Lien, Chung-Cheng; Yang, Chih-Kui, Circuit board structure with capacitors embedded therein.
  2. Asahi,Toshiyuki; Sugaya,Yasuhiro; Komatsu,Shingo; Yamamoto,Yoshiyuki; Nakatani,Seiichi, Component built-in module and method for producing the same.
  3. Gotoh,Masashi; Kawasaki,Kaoru; Nakano,Mutsuko; Yamamoto,Hiroshi, Electronic part manufacturing method and electronic part.
  4. Lien, Chung-Cheng; Yang, Chih-Kui, Method for fabricating circuit board structure with capacitors embedded therein.
  5. Tebbe,Dennis; Smyth,Thomas; Provo,Terry; Ruggiero,Dara, Method of fabricating an RF substrate with selected electrical properties.
  6. Tebbe,Dennis; Smyth,Thomas; Provo,Terry; Ruggiero,Dara, Method of fabricating an RF substrate with selected electrical properties.
  7. Mok, Jee Soo; Yoo, Je Gwang; Lee, Eung Suek; Ryu, Chang Sup, Method of manufacturing printed circuit board.
  8. Tada,Kazuo; Kondo,Koji; Takeuchi,Satoshi, Multi-layer printed circuit board and method for manufacturing the same.
  9. Oh, Yoong; Ryu, Chang-Sup; Park, Dong-Jin; Mok, Jee-Soo; Seo, Byung-Bae, Multilayer printed circuit board using paste bumps.
  10. Kim,Tae Kyoung; Oh,Jun Rok; Kim,Jin Cheol, Printed circuit board having embedded capacitors using hybrid material and method of manufacturing the same.
  11. Mok, Jee-Soo; Ryu, Chang-Sup; Lee, Eung-Suek; Seo, Youn-Soo; Shin, Hee-Bum; Oh, Yoong; Seo, Byung-Bae; Kim, Tae-Kyoung; Park, Dong-Jin, Printed circuit board using paste bump and manufacturing method thereof.
  12. Yamamoto, Kenichi; Komyoji, Daido; Kuramasu, Keizaburo, Sheet-like composite electronic component and method for manufacturing same.

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