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Conformal lining layers for damascene metallization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/52
출원번호 US-0737315 (2003-12-15)
발명자 / 주소
  • Raaijmakers,Ivo
  • Haukka,Suvi P.
  • Saanila,Yille A.
  • Soininen,Pekka J.
  • Elers,Kai Erik
  • Granneman,Ernst H. A.
출원인 / 주소
  • ASM International N.V.
대리인 / 주소
    Knobbe, Martens, Olson &
인용정보 피인용 횟수 : 9  인용 특허 : 40

초록

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flow

대표청구항

What is claimed is: 1. A dual damascene structure in an integrated circuit, comprising; a trench formed in an insulating layer; at least one contact via extending from a floor of the trench downwardly to a conductive element below; and a conductive lining layer along surfaces of the trench and the

이 특허에 인용된 특허 (40)

  1. Conger Darrell R. (Portland OR) Posa John G. (Lake Oswego OR) Wickenden Dennis K. (Lake Oswego OR), Apparatus for depositing material on a substrate.
  2. Gates Stephen McConnell ; Neumayer Deborah Ann, Atomic layer deposition with nitrate containing precursors.
  3. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  4. Lee Ellis,TWX, Dual damascene structure and its manufacturing method.
  5. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with rubidium barrier film and process for making same.
  6. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with strontium barrier film and process for making same.
  7. Wang Chein-Cheng,TWX ; Chang Shih-Chanh,TWX, Fabricating method of glue layer and barrier layer.
  8. Changming Jin ; Kelly J. Taylor ; Wei William Lee, Integrated circuit dielectric and method.
  9. Hoinkis Mark D., Integrated circuits with copper metallization for interconnections.
  10. Huang Richard J. (Milpitas CA) Cheung Robin W. (Cupertino CA) Rakkhit Rajat (Milpitas CA) Lee Raymond T. (Sunnyvale CA), Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC applica.
  11. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  12. Urabe Koji,JPX, Manufacturing method for contact hole.
  13. Iacoponi John A. ; Paton Eric N., Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient.
  14. Posa John G. (Lake Oswego OR), Method and apparatus for producing a constant flow, constant pressure chemical vapor deposition.
  15. Suntola Tuomo,FIX ; Lindfors Sven,FIX ; Soininen Pekka,FIX, Method and equipment for growing thin films.
  16. Kang Sang-bom,KRX ; Chae Yun-sook,KRX ; Park Chang-soo,KRX ; Lee Sang-in,KRX, Method for forming metal layer using atomic layer deposition.
  17. Givens John H. ; Zahorik Russell C. ; Kraus Brenda D., Method for improved metal fill by treatment of mobility layers.
  18. Kim Yeong-kwan,KRX ; Lee Sang-in,KRX ; Park Chang-soo,KRX ; Lee Sang-min,KRX, Method for manufacturing thin film using atomic layer deposition.
  19. Suntola Tuomo S. (Espoo FIX) Pakkala Arto J. (Espoo FIX) Lindfors Sven G. (Espoo FIX), Method for performing growth of compound thin films.
  20. Suntola Tuomo (Riihikallio 02610 Espoo 61 SF) Antson Jorma (Urheilutie 22 ; 01350 Vantaa 35 SF), Method for producing compound thin films.
  21. Kang Sang-Bom,KRX ; Lee Sang-In,KRX, Method of and apparatus for forming a metal interconnection in the contact hole of a semiconductor device.
  22. Sergey D. Lopatin ; Carl Galewski ; Takeshi T. N. Nogami JP, Method of copper interconnect formation using atomic layer copper deposition.
  23. Jing-Cheng Lin TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process.
  24. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of forming a smooth copper seed layer for a copper damascene structure.
  25. Cho Chih-Chen ; Park Kyung-Ho, Method of forming an electrical contact in a substrate.
  26. Zhao, Bin; Brongo, Maureen R., Method of forming dual-damascene interconnect structures employing low-k dielectric materials.
  27. Kang Sang-bom,KRX ; Lim Hyun-seok,KRX ; Chae Yung-sook,KRX ; Jeon In-sang,KRX ; Choi Gil-heyun,KRX, Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor.
  28. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  29. Itoh Hitoshi,JPX, Method of selectively depositing a metal film.
  30. Wang Fei ; Lyons Christopher F. ; Nguyen Khanh B. ; Bell Scott A. ; Levinson Harry J. ; Yang Chih Yuh, Method using a thin resist mask for dual damascene stop layer etch.
  31. Lukanc Todd P. ; Wang Fei ; Avanzino Steven C., Optimized trench/via profile for damascene processing.
  32. Cheung David ; Yau Wai-Fan ; Mandal Robert P. ; Jeng Shin-Puu ; Liu Kuo-Wei ; Lu Yung-Cheng ; Barnes Michael ; Willecke Ralf B. ; Moghadam Farhad ; Ishikawa Tetsuya ; Poon Tze Wing, Plasma processes for depositing low dielectric constant films.
  33. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Process for making a semiconductor device with barrier film formation using a metal halide and products thereof.
  34. Ivo Raaijmakers NL; Pekka T. Soininen FI; Ernst H. A. Granneman NL; Suvi P. Haukka FI, Protective layers prior to alternating layer deposition.
  35. Sneh Ofer, Radical-assisted sequential CVD.
  36. Sergey D. Lopatin ; Carl J. Galewski, Semiconductor catalytic layer and atomic layer deposition thereof.
  37. Mee-Young Yoon KR; Sang-In Lee KR; Hyun-Seok Lim KR, Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer.
  38. Sherman Arthur, Sequential chemical vapor deposition.
  39. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  40. Gadgil Prasad N. ; Seidel Thomas E., Vertically-stacked process reactor and cluster tool system for atomic layer deposition.

이 특허를 인용한 특허 (9)

  1. Raaijmakers, Ivo; Haukka, Suvi P.; Saanila, Ville A.; Soininen, Pekka J.; Elers, Kai-Erik; Granneman, Ernst H.A., Conformal lining layers for damascene metallization.
  2. Riess, Philipp; Kaltalioglu, Erdem; Wendt, Hermann, Devices formed with dual damascene process.
  3. Seutter, Sean M.; Yang, Michael X.; Xi, Ming, Formation of a tantalum-nitride layer.
  4. Pfuetzner, Ronny; Heinrich, Jens, Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material.
  5. La Tulipe, Jr., Douglas C.; Robson, Mark Todhunter, Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias.
  6. La Tulipe, Jr., Douglas C.; Robson, Mark Todhunter, Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias.
  7. LaRoche, Jeffrey R.; Chumbes, Eduardo M.; Ip, Kelly P.; Kazior, Thomas E., Nitride structure having gold-free contact and methods for forming such structures.
  8. LaRoche, Jeffrey R.; Chumbes, Eduardo M.; Ip, Kelly P.; Kazior, Thomas E., Nitride structure having gold-free contact and methods for forming such structures.
  9. Yang, Michael X.; Itoh, Toshio; Xi, Ming, Plasma-enhanced cyclic layer deposition process for barrier layers.
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