IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0117041
(2002-04-05)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg, Woessner &
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인용정보 |
피인용 횟수 :
20 인용 특허 :
147 |
초록
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Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.
대표청구항
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What is claimed: 1. A metal layer in an integrated circuit, comprising: a number of first level vias connecting to a number of devices in a substrate; and a number of first level metal lines formed above and connecting to the number of first level vias; a barrier/adhesion layer having a thickness
What is claimed: 1. A metal layer in an integrated circuit, comprising: a number of first level vias connecting to a number of devices in a substrate; and a number of first level metal lines formed above and connecting to the number of first level vias; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias, the barrier/adhesion layer including one or more materials selected from zirconium or hafnium; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines. 2. The metal layer of claim 1, wherein the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms includes hafnium. 3. The metal layer of claim 1, wherein the number of first level vias connecting to a number of silicon devices in a substrate are surrounded by an insulator layer. 4. The metal layer of claim 1, wherein the barrier/adhesion layer formed on the number of first level vias metal lines is surrounded by a polyimide insulator layer. 5. The metal layer of claim 1, wherein the number of first level metal lines includes a number of first level metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold. 6. A metal layer in an integrated circuit, comprising: a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure comprising: a layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms; a first layer of Aluminum on the layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms; a layer of Copper on the first layer of Aluminum having a thickness of approximately 10 Angstroms; and a second layer of Aluminum on the layer of Copper having a thickness of approximately 50 Angstroms. 7. The metal layer of claim 6, wherein the insulator layer includes Si3N4 having a thickness between about 100 Å to about 500 Å. 8. The metal layer of claim 6, wherein the oxide layer includes a fluorinated silicon oxide layer. 9. A metal interconnect in an integrated circuit, comprising: a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure comprising: a layer of tantalum and CuTi, the layer having a thickness of approximately 5 to 100 Angstroms disposed on a first level via of the number of first level vias; a seed layer of Copper on the layer of tantalum and CuTi, the seed layer having a thickness of approximately 100 Angstroms; and a copper metal line formed on the seed layer of copper. 10. The metal layer of claim 9, wherein each conductive structure further includes a layer of tantalum nitride forming a top surface of each conductive structure such that the top surface of each conductive structure is level with the top surface of the oxide layer. 11. The metal interconnect of claim 9, wherein at least one of the number of first level vias is a tungsten via. 12. The metal interconnect of claim 9, wherein at least one of the number of first level vias is within a titanium silicide liner. 13. A metal interconnect in an integrated circuit, comprising: a first level via in a first insulator layer connecting to a device in a substrate; and an oxide layer formed over the first level via in the first insulator layer, wherein the oxide layer includes a conductive structure connecting from a top surface of the oxide layer to the first level via, the conductive structure including: a barrier/adhesion layer having two material layers, the barrier/adhesion layer disposed on a first level via of the number of first level vias; a seed layer on the barrier/adhesion layer; a layer of aluminum on the seed layer, the layer of aluminum having a thickness of about 50 Angstroms; and a metal line formed on the layer of aluminum. 14. The metal interconnect of claim 13, wherein the barrier/adhesion layer has a thickness of approximately 5 to 100 Angstroms. 15. The metal interconnect of claim 13, wherein the barrier/adhesion layer includes material selected from the group consisting of titanium, zirconium, and hafnium. 16. The metal interconnect of claim 13, wherein the seed layer includes material selected from a group consisting of silver and gold. 17. The metal interconnect of claim 13, wherein the first level via includes tungsten and is contained in a liner. 18. The metal interconnect of claim 13, wherein the first level via is contained in a liner that separates the first level via from a layer of Si3N4. 19. The metal interconnect of claim 13, wherein the seed layer has a thickness of approximately 10 Angstroms. 20. A metal interconnect in an integrated circuit, comprising: a first level via in a first insulator layer connecting to a device in a substrate; a titanium silicide liner that contains the first level via; and a conductive structure formed over the first level via in the first insulator layer, the conductive structure including: a barrier/adhesion layer disposed on the first level via; a seed layer on the barrier/adhesion layer; and a metal line disposed above the seed layer. 21. The metal interconnect of claim 20, wherein the barrier/adhesion layer has a thickness in the range of 5 to 150 Angstroms. 22. The metal interconnect of claim 20, wherein the barrier/adhesion layer includes CuTi. 23. The metal interconnect of claim 20, further including a layer of aluminum between the seed layer and the metal line. 24. The metal interconnect of claim 20, wherein the conductive structure is contained within a fluorinated silicon oxide layer. 25. A metal interconnect in an integrated circuit, comprising: a first level via in a first insulator layer connecting to a device in a substrate; a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including: a first barrier/adhesion layer disposed on the first level via the first barrier/adhesion layer including one or more materials selected from zirconium, hafnium, or CuTi; a first seed layer disposed on the first barrier/adhesion layer; and a first metal line disposed above the first seed layer; a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including: a second barrier/adhesion layer disposed on the first metal line; a second seed layer disposed on the second barrier/adhesion layer; and a second metal line disposed above the second seed layer. 26. The metal interconnect of claim 25, further including a layer of aluminum between the first seed layer and the first metal line. 27. The metal interconnect of claim 25, further including a layer of aluminum between the second seed layer and the second metal line. 28. The metal interconnect of claim 25, wherein the first metal line and the second metal line are composed of different materials. 29. The metal interconnect of claim 25, wherein the first metal line and the second metal line each include material selected from a group consisting of copper, aluminum, silver, and gold. 30. The metal interconnect of claim 25, wherein the first and the second seed layers include material selected from the group consisting of aluminum, copper, silver, and gold. 31. The metal interconnect of claim 25, wherein the first and the second barrier/adhesion layers each have a thickness in the range of 5 to 150 Angstroms. 32. The metal interconnect of claim 25, wherein the first and second barrier/adhesion layers each include zirconium. 33. A metal interconnect in an integrated circuit, comprising: a first level via in a first insulator layer connecting to a device in a substrate; a liner containing the first level via; a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including: a first barrier/adhesion layer disposed on the first level via, the first barrier/adhesion layer including one or more materials selected from zirconium, hafnium, or CuTi; a first seed layer disposed on the first barrier/adhesion layer; and a first metal line disposed above the first seed layer; a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including: a second barrier/adhesion layer disposed on the first metal line; a second seed layer disposed on the second barrier/adhesion layer; and a second metal line disposed above the second seed layer. 34. The metal interconnect of claim 33, wherein the liner contains titanium silicide. 35. The metal interconnect of claim 33, wherein the liner separates the via from a layer of Si3N4. 36. The metal interconnect of claim 33, wherein the first metal line and the second metal line each include material selected from a group consisting of copper, aluminum, silver, and gold. 37. The metal interconnect of claim 33, wherein the first and second barrier/adhesion layers each have a thickness in the range of 5 to 150 Angstroms. 38. The metal interconnect of claim 33, wherein the first and second barrier/adhesion layers each include material selected from the group consisting of zirconium or hafnium.
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