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A fault handling system for short circuit recovery in three-phase multiple-level inverter bridges, used to drive inductive loads, which waits for either desaturation of switches or expiration of a delay period based upon an amount of time before saturated switches are damaged before commanding off s

A fault handling system for short circuit recovery in three-phase multiple-level inverter bridges, used to drive inductive loads, which waits for either desaturation of switches or expiration of a delay period based upon an amount of time before saturated switches are damaged before commanding off switches that are saturated, and which artificially creates a dead-short across the three-phase output to force switches conducting a fault current to desaturate. By delaying the switching-off of the inverter bridge during a fault, waiting for desaturation to occur, the statistical likelihood of switch survival is improved.

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What is claimed is: 1. A method of controlling a three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bu

What is claimed is: 1. A method of controlling a three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bus voltage and one of the L levels is a most-positive bus voltage, each branch comprising two half-branches, a first one-half branch comprising transistor switches connected between the most-positive bus voltage and a respective phase output, and a second one-half branch comprising transistor switches connected between the most-negative bus voltage and the respective phase output, wherein within a half-branch, outer is defined as toward the most-positive or most-negative bus voltage, and inner is defined as toward the phase output, wherein for each branch, the method comprises: comparing a magnitude of an instantaneous output current (Io) of a phase of the three-phase output of the inverter bridge with a rated nominal current of a transistor switch (INom) of the transistor switches of the branch plus an overload current threshold (IOL), wherein IOL+INom satisfies Imax >IOL+INOM≧INom, Imax being a maximum rated current of the transistor switches of the branch; in response to comparing Io with INom+I OL, if |Io|>INom+IOL, then for each one-half branch of said branch: identifying transistor switches of the half branch that are conducting the instantaneous output current (Io) exceeding I Nom+IOL; securing an off-state to transistor switches of the half branch that are identified as being in an off-state; sequentially turning off transistor switches in the half branch that are not conducting the instantaneous output current (I o) exceeding INom+IOL; comparing the instantaneous output current (Io) exceeding INom+IOL with Imax, and if |I o|≦Imax, sequentially commanding all transistor switches of the half-branch remaining in an on-state to assume an off-state, while continuing to compare for |Io|>Imax; and until a time elapsed after said step of sequentially commanding exceeds toff, continuing to compare for |Io |>Imax, wherein toff is defined as a rated turn-off time of the transistor switches which is a sum of a turn-off delay time plus current fall-time, and if |Io|>Imax, checking a most outer transistor switch remaining in an on-state for desaturation, and if not desaturated, keeping the most outer transistor switch remaining in an on-state and any transistor switches between the most outer transistor switch and the phase output in an on-state, and if the most outer transistor switch and any transistor switches between the most outer transistor switch and the phase output have been commanded to an off-state, then commanding these transistor switches back to an on-state, and then delaying until a sooner of desaturation of the most outer transistor switch remaining in an on-state, expiration of a delay period based upon an amount of time before the most outer transistor remaining in an on-state is damaged, and |Io|<Imax; and if the most outer transistor switch is desaturated, when said delay period expires, or |Io|<Imax, turning off the most outer transistor switch remaining in an on-state, and then if any transistor switches of the half-branch remain in an on-state, repeating the method from said step of comparing the instantaneous output current (Io) exceeding INom+IOL with Imax. 2. A method according to claim 1, said step of checking a most outer transistor switch remaining in an on-state for desaturation comprises determining whether a voltage across the transistor switch is above a rated saturation voltage of the transistor switch. 3. A method according to claim 1, wherein said delay period corresponds to a time for a temperature of the most outer transistor switch remaining in an on-state to reach a maximum rated temperature value. 4. A method according to claim 1, wherein said transistor switches are insulated gate bipolar transistors (IGBTs) or bipolar junction transistors (BJTs), and said step of checking a most outer transistor switch remaining in an on-state for desaturation comprises determining whether the collector-to-emitter voltage (Vce) of the transistor switch is above a rated saturation collector-to-emitter voltage (Vce sat ) of the transistor switch, the transistor switch being not desaturated if Vce≦Vce sat and being desaturated if Vce>Vce sat. 5. A method according to claim 4, wherein said delay period corresponds to a time for a temperature of the most outer transistor switch remaining in an on-state to reach a maximum rated temperature value, and is determined by: wherein: Vce max is defined as a maximum rated collector-to-emitter voltage across a transistor switch remaining in an on-state, and Isc is defined as a maximum rated short circuit current per transistor switch. 6. A method according to claim 4, wherein said delay period corresponds to a time for a temperature of the most outer transistor switch remaining in an on-state to reach a maximum rated temperature value, and approximately equals: wherein: Vce max is defined as a maximum rated collector-to-emitter voltage across the transistor switch remaining in an on-state, and tsc max is defined as a rated maximum short-circuit time duration which the transistor switch can withstand when submitted to Vce max and Isc. 7. A method according to claim 1, wherein the method further comprises: when said delay period expires without the most outer transistor remaining in an on-state desaturating, prior to turning off the most outer transistor, shunting the phase output provided by the half-branch to a neutral level if not already shunted to a neutral voltage level, wherein the neutral voltage level is a difference of the most-positive bus voltage and the most-negative bus voltage, divided by two. 8. A method according to claim 7, wherein: when the half-branch is a first one-half branch, said step of shunting the phase output to the neutral level shunts first one-half branches of all three branches of the three-phase inverter bridge, and when the half branch is a second one-half branch, said step of shunting the phase output to the neutral level shunts second one-half branches of all three branches of the three-phase inverter bridge. 9. A method according to claim 7, wherein said step of shunting the phase output to the neutral level shunts all half-branches of all three branches of the three-phase inverter bridge. 10. A storage medium storing a set of program instructions for a controller, the controller being configured to control a three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bus voltage and one of the L levels is a most-positive bus voltage, each branch comprising two half-branches, a first one-half branch comprising transistor switches connected between the most-positive bus voltage and a respective phase output, and a second one-half branch comprising transistor switches connected between the most-negative bus voltage and the respective phase output, wherein within a half-branch, outer is defined as toward the most-positive or most-negative bus voltage, and inner is defined as toward the phase output, the set of program instructions, when executed by the controller, causing the controller to perform the following steps for each branch the three-phase inverter bridge: comparing a magnitude of an instantaneous output current (Io) of a phase of the three-phase output of the inverter bridge with a rated nominal current of a transistor switch (INom) of the transistor switches of the branch plus an overload current threshold (IOL), wherein IOL+INom satisfies Imax >IOL+INOM≧INom, Imax being a maximum rated current of the transistor switches of the branch; in response to comparing Io with INom+I OL, if |Io|>INom+IOL, then for each one-half branch of said branch: identifying transistor switches of the half branch that are conducting the instantaneous output current (Io) exceeding I Nom+IOL; securing an off-state to transistor switches of the half branch that are identified as being in an off-state; sequentially turning off transistor switches in the half branch that are not conducting the instantaneous output current (I o) exceeding INom+IOL; comparing the instantaneous output current (Io) exceeding INom+IOL with Imax, and if |I o|≦Imax, sequentially commanding all transistor switches of the half-branch remaining in an on-state to assume an off-state, while continuing to compare for |Io|>Imax; and until a time elapsed after said step of sequentially commanding exceeds toff, continuing to compare for |Io |>Imax, wherein toff is defined as a rated turn-off time of the transistor switches which is a sum of a turn-off delay time plus current fall-time, and if |Io|>Imax, checking a most outer transistor switch remaining in an on-state for desaturation, and if not desaturated, keeping the most outer transistor switch remaining in an on-state and any transistor switches between the most outer transistor switch and the phase output in an on-state, and if the most outer transistor switch and any transistor switches between the most outer transistor switch and the phase output have been commanded to an off-state, then commanding these transistor switches back to an on-state, and then delaying until a sooner of desaturation of the most outer transistor switch remaining in an on-state, expiration of a delay period based upon an amount of time before the most outer transistor remaining in an on-state is damaged, and |Io|<Imax; and if the most outer transistor switch is desaturated, when said delay period expires, or |Io|<Imax, turning off the most outer transistor switch remaining in an on-state, and then if any transistor switches of the half-branch remain in an on-state, repeating from the step of comparing the instantaneous output current (Io) exceeding INom+IOL with I max. 11. A storage medium storing a set of program instructions for a controller according to claim 10, wherein said delay period corresponds to a time for a temperature of the most outer transistor switch remaining in an on-state to reach a maximum rated temperature value. 12. A storage medium storing a set of program instructions for a controller according to claim 10, the set of program instructions, when executed by the controller, further causing the controller to perform the following step: when said delay period expires without the most outer transistor remaining in an on-state desaturating, prior to turning off the most outer transistor, shunting the phase output provided by the half-branch to a neutral level if not already shunted to a neutral voltage level, wherein the neutral voltage level is a difference of the most-positive bus voltage and the most-negative bus voltage, divided by two. 13. A three-phase inverter controller for controlling a three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bus voltage and one of the L levels is a most-positive bus voltage, each branch comprising two half-branches, a first one-half branch comprising transistor switches connected between the most-positive bus voltage and a respective phase output, and a second one-half branch comprising transistor switches connected between the most-negative bus voltage and the respective phase output, wherein within a half-branch, outer is defined as toward the most-positive or most-negative bus voltage, and inner is defined as toward the phase output, for each branch, the controller comprising at least a first comparison circuit, a second comparison circuit, a delay circuit, and logic circuitry, the first comparison circuit comparing a magnitude of an instantaneous output current (Io) of a phase of the three-phase output of the inverter bridge with a rated nominal current (INom) of the transistor switches of the branch plus an overload current threshold (IOL), wherein IOL+INOM satisfies Imax>IOL+INom≧INom , Imax being a maximum rated current of the transistor switches of the branch, wherein, if |Io|>INom+IOL, then the logic circuitry: identifies transistor switches of the branch that are conducting the instantaneous output current (Io) exceeding I Nom+IOL; secures an off-state to transistor switches that are identified as being in an off-state; sequentially, from outer-to-inner, commands off transistor switches within a half-branch containing transistor switches that have an on-state but are not conducting the instantaneous output current (I o) exceeding INom+IOL; the second comparison circuit comparing the instantaneous output current (Io) with Imax, wherein while |Io|>INom+IOL and |Io|≦Imax, the logic circuitry: sequentially, from outer-to-inner, commands all transistor switches remaining in an on-state to assume an off-state; and wherein while |Io|>Imax, the logic circuitry: determines whether a most outer transistor switch remaining in an on-state is desaturated, and if the outer transistor switch remaining in an on-state is desaturated, then the logic circuitry: keeps the most outer transistor switch remaining in an on-state and any transistor switches between the most outer transistor switch and the phase output in an on-state, and if the most outer transistor switch and any transistor switches between the most outer transistor switch and the phase output have been commanded to an off-state, then commanding these transistor switches back to an on-state, and then waits until a sooner of desaturation of the most outer transistor switch remaining in an on-state, expiration of a delay period of the delay circuit, the delay period being based upon an amount of time before the most outer transistor remaining in an on-state is damaged, and |Io|<Imax; and if most outer transistor switch remaining in an on-state is desaturated, when said delay period expires, or |Io|<I max, then the logic circuitry: turns off the most outer transistor switch remaining in an on-state, after which, a next most outer transistor switch, if any, remaining in an on-state is checked for desaturation. 14. A three-phase-level inverter controller according to claim 13, wherein the logic circuitry checks whether a most outer transistor switch remaining in an on-state is desaturated by checking a signal received from a driver card driving the most outer transistor switch. 15. A three-phase-level inverter controller according to claim 13, wherein the delay period of the delay circuit is set so that expiration of the delay period corresponds to a time for a temperature of the most outer transistor switch remaining in an on-state to reach a maximum rated temperature value. 16. A three-phase-level inverter controller according to claim 13, wherein the first comparison circuit comprises a first comparator, and the second comparison circuit comprises a second comparator. 17. A crowbar circuit for protecting transistor switches of a three-phase inverter bridge when a short occurs and at least one of the transistor switches is allowed to saturate due to a short-circuit inductance, the three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bus voltage and one of the L levels is a most-positive bus voltage, any intermediate bus voltage levels if (L>2) being differentiated from other bus voltage levels by a difference of the most-positive bus voltage and the most-negative bus voltage, divided by (L-1), the crowbar circuit comprising: at least one switch, selectively shunting each phase of the three-phase output of the inverter bridge to a neutral voltage level, the neutral voltage level being a difference of the most-positive bus voltage and the most-negative bus voltage, divided by two, wherein, by closing said at least one switch, selectively shunting each phase to the neutral voltage, saturated transistor switches of the three-phase inverter bridge become desaturated. 18. A crowbar circuit according to claim 17, wherein if "L" is an odd number, the neutral voltage level is one of the "L" bus voltage levels of the inverter bridge, and wherein if "L" is an even number, the neutral voltage level is between two of the "L" bus voltage levels of the inverter bridge. 19. A crowbar circuit according to claim 17, wherein the crowbar circuit is provided within a separate housing from the three-phase inverter bridge, configured to be electrically connected to the three-phase output of the inverter bridge. 20. A crowbar circuit according to claim 17, wherein said at least one switch comprises a first switch and a second switch, the crowbar circuit further comprising: a first set of three diodes, each diode of the first set having an anode connected to a respective phase output of the three-phase output of the inverter bridge, cathodes of the first set of three diodes being connected to said first switch, said first switch selectively shunting a first half-wave rectified portion of the three-phase output to the neutral voltage level, and a second set of three diodes, each diode of the second set having a cathode connected to a respective phase output of the three-phase output of the inverter bridge, anodes of the second set of three diodes being connected to said second switch, said second switch selectively shunting a second half-wave rectified portion of the three-phase output to the neutral voltage level. 21. A crowbar circuit according to claim 20, wherein the first and second switch are configured to be closed collectively. 22. A crowbar circuit according to claim 20, wherein the first and second switch are configured to be closed individually. 23. A method of protecting transistor switches of a three-phase inverter bridge when a short occurs and at least one of the transistor switches is allowed to saturate due to a short-circuit inductance, the three-phase inverter bridge having three branches, each branch providing one phase of a three-phase output for driving an inductive load, the inverter bridge having "L" bus voltage levels (L≧2), wherein one of the L levels is a most-negative bus voltage and one of the L levels is a most-positive bus voltage, the method comprising: detecting a short-circuit by comparing output currents of each phase of the three-phase output of the inverter bridge with a threshold level; in each branch providing one of the three-phase outputs in which a short-circuit is detected, determining whether each transistor switch of the branch having an on-state is saturated, and if it is determined that at least one transistor switch is saturated, shunting the phase corresponding to the branch to a neutral voltage level, the neutral voltage level being a difference of the most-positive bus voltage and the most-negative bus voltage, divided by two. 24. A method according to claim 23, wherein each branch of the inverter bridge comprises two half-branches, a first one-half branch comprising transistor switches connected between the most-positive bus voltage and the phase output, and a second one-half branch comprising transistor switches connected between the most-negative bus voltage and the phase output, said method further comprising: wherein when a saturated transistor switch is in one of the first one-half branches of the inverter bridge, said step of shunting comprises: shunting that portion of the phase output having a more-positive bus voltage level than the neutral voltage level to the neutral voltage level; and wherein when a saturated transistor switch is in one of the second one-half branches of the inverter bridge, said step of shunting comprises: shunting that portion of the phase output having a more-negative voltage level than the neutral voltage level to the neutral voltage level. 25. A method according to claim 23, wherein said shunting comprises: shunting that portion of the phase output having a more-positive bus voltage level than the neutral voltage level to the neutral voltage level; and shunting that portion of the phase output having a more-negative voltage level than the neutral voltage level to the neutral voltage level.