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Global processor resource assignment in an assembler 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0340499 (2003-01-10)
발명자 / 주소
  • Garvey,Joseph F.
  • Jeffries,Clark D.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Sawyer Law Group LLP
인용정보 피인용 횟수 : 7  인용 특허 : 34

초록

An assembler for assembling code is disclosed. The assembly language code includes a plurality of code blocks associated with resource-needs, such as variables, and resources, such as registers, I/O locations, memory locations, and coprocessors. A technology is provided that allows the global assign

대표청구항

What is claimed is: 1. A method for assembling assembly language code using an assembler, the code including a plurality of code blocks, the plurality of code blocks having a plurality of resource-needs and the plurality of code blocks having a plurality of resources, the method comprising the step

이 특허에 인용된 특허 (34)

  1. Barkans Anthony C. (Fort Collins CO) Swanson Roger (Fort Collins CO), Allocation of resources of a pipelined processor by clock phase for parallel execution of dependent processes.
  2. Lind, Michael A.; Priddy, Kevin L.; Morgan, Gary B.; Griffin, Jeffrey W.; Ridgway, Richard W.; Stein, Steven L., Application specific intelligent microsensors.
  3. Hattori Naoki,JPX, Assembler device and its assembling method for use in a microcomputer or other computer system.
  4. Mizuse Harumi (Tokyo JPX) Kawata Kazuhide (Tokyo JPX), Assembler system for determining when to compile source code modules.
  5. Heddes, Marco C.; Leavens, Ross Boyd; Rinaldi, Mark Anthony, Assembler tool for processor-coprocessor computer systems.
  6. Munshi Ashfaq A. (San Jose CA) Schimpf Karl M. (Santa Cruz CA), Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic bl.
  7. Ewart Graham W.,CAX, Compile-time data dependency verification.
  8. Utsumi Isao (Tokyo JPX) Mori Yoshikazu (Tokyo JPX), Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of as.
  9. Willis John Christopher ; Newshutz Robert Neill, Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models.
  10. Austin Paul F., Data acquisition system with collection of hardware information for identifying hardware constraints during program deve.
  11. Burrows Michael ; Nelson Charles G. ; Savage Stefan ; Sobalvarro Patrick G., Detecting concurrency errors in multi-threaded programs.
  12. Crelier Regis ; Cantey James Lee, Development system and methods with direct compiler support for detecting invalid use and management of resources and me.
  13. Cantey James Lee ; Crelier Regis, Development system with methods for detecting invalid use and management of resources and memory at runtime.
  14. Kuno Michiaki,JPX, Device for generating source programs of multiple kinds of assembler languages from extended tree structure chart by applying the same source generation rules.
  15. Richard A. Lethin ; Joseph A. Bank, III ; Charles D. Garrett ; Mikayo Wada JP; Mitsuo Sakurai JP, Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method.
  16. Baumgart, Leona Dryden; Ehrman, John Robert; Lee, Richard E.; Lee, Barbara Ann, Extended syntax record for assembler language instructions.
  17. Taylor Brad (Oakland CA), Implementation of a selected instruction set CPU in programmable hardware.
  18. Wallace David R., Method and apparatus for conflict-based block reordering.
  19. Goebel Kurt J., Method and apparatus for easy insertion of assembler code for optimization.
  20. Salil Pradhan ; Mark D. Hennecke ; Michey N Mehta ; Ruslan Meshenberg, Method and apparatus for pre-allocation of system resources to facilitate garbage collection.
  21. Kevorkian Aram K. (La Jolla CA), Method and apparatus for pre-processing inputs to parallel architecture computers.
  22. Van Praet Johan Roland,BEX ; Lanneer Dirk,BEX ; Geurts Werner Gustaaf Theresia,BEX ; Goossens Gert Lodewijk Huibrecht,BEX, Method of generating code for programmable processors, code generator and application thereof.
  23. Scales Daniel J., Method of reducing the number of overhead instructions by modifying the program to locate instructions that access share.
  24. Berkovich Semyon (11918 Stonewood La. Rockville MD 20852) Berkovich Efraim (11918 Stonewood La. Rockville MD 20852), Methods and apparatus for concurrent execution of serial computing instructions using combinatorial architecture for pro.
  25. Kelleher Brian Michael, Parallel-processor graphics architecture.
  26. Buckler Andrew J. (Ontario NY) Roland Richard A. (Fairport NY) Nerkowski Christopher W. (Rochester NY), Production control system and method.
  27. Thornley, John; Chandy, K. Mani; Ishii, Hiroshi, Programming system and thread synchronization mechanisms for the development of selectively sequential and multithreaded computer programs.
  28. Loen, Larry Wayne; Santosuosso, John Matthew, Safe strength reduction for Java synchronized procedures.
  29. Rentschler Eric ; Krech ; Jr. Alan S. ; Scott Noel D., System and method for dynamically allocating data among geometry accelerators in a computer graphics system.
  30. Sastry Shivakumar, System for and method of allocating processing tasks of a control program configured to control a distributed control system.
  31. Imai Toru (Kanagawa JPX) Sirakawa Kenji (Kanagawa JPX), System for compiling iterated loops based on the possibility of parallel execution.
  32. Mortson Douglas J. (Bradford CAX), Use of build status indicators in connection with building of complex computer programs from source code parts.
  33. Scales Daniel J., Validation checking of shared memory accesses.
  34. Bowman-Amuah, Michel K., View configurer in a presentation services patterns environment.

이 특허를 인용한 특허 (7)

  1. Dobbins, Kris A; Swingle, David N, Macro to instantiate a variable used with a first macro requiring use of a second macro suitable for said variable.
  2. Dobbins,Kris A.; Swingle,David N., Macros to support structures for an assembler that does not support structures.
  3. Bussa, Vinod; Choudhury, Shubhodeep Roy; Dusanapudi, Manoj; Hatti, Sunil Suresh; Kapoor, Shakti; Satyanarayana, Batchu Naga Venkata, System and method for efficiently testing cache congruence classes during processor design verification and validation.
  4. Choudhury, Shubhodeep Roy; Dusanapudi, Manoj; Hatti, Sunil Suresh; Kapoor, Shakti; Moharil, Rahul Sharad, System and method for generating fast instruction and data interrupts for processor design verification and validation.
  5. Anvekar, Divya Subbarao; Choudhury, Shubhodeep Roy; Dusanapudi, Manoj; Hatti, Sunil Suresh; Kapoor, Shakti, System and method for testing a large memory area during processor design verification and validation.
  6. Arora, Sampan; Choudhury, Shubhodeep Roy; Dusanapudi, Manoj; Hatti, Sunil Suresh; Kapoor, Shakti; Mohanan, Sai Rupak, System and method for testing multiple processor modes for processor design verification and validation.
  7. Choudhury, Shubhodeep Roy; Dusanapudi, Manoj; Hatti, Sunil Suresh; Kapoor, Shakti; Moharil, Rahul Sharad, System and method for using resource pools and instruction pools for processor design verification and validation.
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