초록 ▼

An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive

An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

대표청구항 ▼

What is claimed is: 1. A data processing apparatus for generating an object code from a source code descriptive of operation of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instruc

What is claimed is: 1. A data processing apparatus for generating an object code from a source code descriptive of operation of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to said individually established operation instructions, said object code containing at least contexts composed of said individually established operation instructions for sequentially switched operation cycles of said processing circuits and said interconnection circuits, said data processing apparatus comprising: condition storage means for registering, in advance, limiting conditions representing at least a physical structure and physical characteristics of said parallel operation apparatus; source input means for entering said source code; object generating means for detecting operation states in successively transited stages corresponding to said contexts in the sequentially switched operation cycles from said source code entered by said source input means according to said limiting conditions, and generating said object code; and object output means for outputting said object code generated by said object generating means. 2. A data processing apparatus according to claim 1, wherein said parallel operation apparatus comprises a matrix circuit having said matrix of processing circuits and interconnection circuits, and a state manager, separate from said matrix circuit, for sequentially switching the contexts of said matrix circuit in the operation cycles, respectively; said object generating means comprising means for separating a data path corresponding to said matrix circuit and a finite-state machine corresponding to said state manager from each other when said object code is generated from said source code according to said limiting conditions. 3. A data processing apparatus according to claim 2, wherein said object generating means comprises: graph generating means for analyzing a language of said source code and generating a Data Flow Graph (DFG); and schedule generating means for generating a Control Data Flow Graph (CDFG) in which said operation states sequentially transited in a plurality of stages are scheduled, from the DFG generated by said graph generating means according to said limiting conditions. 4. A data processing apparatus according to claim 1, wherein said object generating means comprises: graph generating means for analyzing a language of said source code and generating a Data Flow Graph (DFG); and schedule generating means for generating a Control Data Flow Graph (CDFG) in which said operation states sequentially transited in a plurality of stages are scheduled, from the DFG generated by said graph generating means according to said limiting conditions. 5. A data processing apparatus according to claim 4, wherein said condition storage means comprises means for registering, as said limiting conditions, a predetermined threshold value corresponding to at least a number of said processing circuits; wherein said graph generating means comprises means for generating said DFG in which a plurality of data processing are associated with each other based on a cause-and-effect relationship, from said source code; and wherein said schedule generating means comprises means for scheduling data processing processes of said DFG for said operation states in a plurality of stages in a sequence corresponding to said cause-and-effect relationship, and shifting the operation states to a next stage each time a number of the scheduled data processing processes exceeds said predetermined threshold value. 6. A data processing apparatus according to claim 5, wherein said condition storage means comprises means for registering, as said limiting conditions, a bit number of processing data of said processing circuits; said graph generating means comprising means for generating said DFG in which the bit number of the processing data is set in the data processing, from said source code; and said schedule generating means comprising means for calculating a number of processing circuits to be used in said data processing processes scheduled for the operation states, respectively, according to said bit number, and subtracting the calculated number from said predetermined threshold value. 7. A data processing apparatus according to claim 4, wherein said condition storage means comprises means for registering, as said limiting conditions, delay times of said processing circuits and said interconnection circuits and a time required by said operation cycles; said schedule generating means comprising means for scheduling the data processing of said DFG in said operation states in a plurality of stages in a sequence corresponding to a cause-and-effect relationship, and shifting the operation states to a next stage each time an accumulated value of said delay times of said processing circuits and said interconnection circuits used in the scheduled data processing exceeds said time required by said operation cycles. 8. A data processing apparatus according to claim 4, wherein said parallel operation apparatus comprises a matrix circuit having said matrix of processing circuits and interconnection circuits, for storing said contexts of said object code up to a predetermined number and sequentially performing corresponding processes, and a state manager, separate from said matrix circuit, for updating the context for which a corresponding process has been executed into a new context while said matrix circuit is performing the corresponding process in one of said predetermined number of contexts stored in said matrix circuit; said schedule generating means comprising means for generating said CDFG in order for said state manager to update the context for which a corresponding process has been executed into a new context while said matrix circuit is performing the corresponding process in one of said predetermined number of contexts stored in said matrix circuit. 9. A data processing apparatus according to claim 4, wherein said parallel operation apparatus comprises a matrix circuit having said matrix of processing circuits and interconnection circuits, and a state manager, separate from said matrix circuit, for sequentially switching the contexts of said matrix circuit in the operation cycles, respectively, and description generating means for generating an RTL (Register Transfer Level) description in the operation states in a plurality of stages, separately for said matrix circuit and said state manager, from said CDFG generated by said schedule generating means according to said limiting conditions. 10. A data processing apparatus according to claim 9, wherein said object generating means comprises list generating means for generating net lists of said processing circuits in the respective operation states in a plurality of stages from the RTL description of said matrix circuit generated by said description generating means according to said limiting conditions. 11. A data processing apparatus according to claim 9, wherein each of said processing circuits of said parallel operation apparatus comprises a plurality of types of circuit resources for which processing data have different bit numbers; and said object generating means comprising list generating means for generating net lists of said plurality of types of circuit resources of said processing circuits in the respective operation states in a plurality of stages from the RTL description of said matrix circuit generated by said description generating means according to said limiting conditions. 12. A data processing apparatus according to claim 11, wherein said parallel operation apparatus comprises a matrix circuit having said matrix of processing circuits and interconnection circuits, and a state manager, separate from said matrix circuit, for sequentially switching contexts of said matrix circuit in operation cycles, respectively, data processing apparatus further comprising: object storage means for registering, in advance, various object codes of said state manager which correspond to the operation states in a plurality of stages; state converting means for converting the RTL description of said state manager generated by said description generating means into the corresponding object codes according to the net lists of said matrix circuit which have been generated by said list generating means; and object output means for outputting the object codes of said state manager which have been converted by said state converting means. 13. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code stored in code storage means, said object code being generated by a data processing apparatus according to claim 12. 14. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by a data processing apparatus according to claim 12. 15. A data processing system comprising: a data processing apparatus according to claim 12; and a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by said data processing apparatus. 16. A data processing apparatus according to claim 11, wherein each of said processing circuits of said parallel operation apparatus comprises mb circuit resources for which processing data comprises mb(m-(bit)) data where "m" represents a natural number of "2" or greater and nb circuit resources for which processing data comprises nb(n-(bit)) data where "n" represents a natural number smaller than "m"; and said list generating means comprising means for generating net lists of m/nb circuit resources of said processing circuits from said RTL description according to said limiting conditions. 17. A data processing apparatus according to claim 16, wherein said list generating means comprises means for assigning "xb(x-(bit))" data processing, where "x" is a natural number greater than "m", of said RTL description to Y mb circuit resources and Z nb circuit resources where: x=Ym+Zn ("Y" and "Z" are a natural number). 18. A data processing apparatus according to claim 17, wherein said list generating means comprises means for calculating an integer "Y" of a result produced by dividing "x" by "m", and calculating an integer "Z" of a result produced by dividing a remainder by "n". 19. A data processing apparatus according to claim 18, wherein said list generating means comprises means for calculating said integer "Z" if said remainder is smaller than a predetermined threshold value, and adding "1" to "Y" to make "Z=0" if said remainder is equal to or greater than said predetermined threshold value. 20. A data processing apparatus according to claim 17, wherein "nb" of said limiting conditions registered in said condition storage means comprises "1 (bit)". 21. A data processing apparatus according to claim 11, further comprising: object storage means which comprises a means for registering, in advance, various object codes of said processing circuits; processing layout means for assigning said net lists generated by said list generating means to said processing circuits of said matrix circuit in the respective contexts in a plurality of cycles according to said limiting conditions; and code converting means for converting the net lists assigned to said processing circuits by said processing layout means into corresponding object codes. 22. A data processing apparatus according to claim 21, said object storage means comprises means for registering, in advance, various object codes of said interconnection circuits, further comprising: interconnection converting means for converting said net lists of said interconnection circuits into object codes according to the object codes of said processing circuits which have been converted by said code converting means. 23. A data processing apparatus according to claim 22, wherein each of said processing circuits has a register file for temporarily holding processing data; said processing layout means comprising means for commonly assigning said net lists associated with said processing data in the respective contexts in a plurality of successive cycles to said register files in a given position in said matrix circuit. 24. A data processing apparatus according to claim 23, wherein said processing layout means comprises means for first assigning said net lists to said register files irrespective of the association of said processing data in respective contexts in a plurality of cycles, and then adjusting assigned positions to align the positions of said register files to which said net lists associated with said processing data are assigned, in the contexts in a plurality of consecutive cycles. 25. A data processing apparatus according to claim 23, wherein said processing layout means comprises means for first fixing positions in said matrix circuit of said register files to which said net lists associated with said processing data are commonly assigned in the respective contexts in a plurality of cycles, and then assigning other net lists to other register files in the respective contexts in a plurality of cycles. 26. A data processing apparatus according to claim 23, wherein said processing layout means comprises means for first setting the relative positions in said matrix circuit of said register files to which said net lists associated with said processing data are commonly assigned in the respective contexts in a plurality of cycles, and then assigning other net lists to other register files in the respective contexts in a plurality of cycles while maintaining the relative positions. 27. A data processing apparatus according to claim 1, further comprising: state detecting means for detecting a plurality of operation states to be assigned to one of the contexts from said operation states in a plurality of successively transited stages according to said limiting conditions; and state combining means for assigning the operation states detected by said state detecting means to one of said contexts. 28. A data processing apparatus according to claim 27, wherein said state detecting means comprises means for detecting a plurality of operation states in successive transition stages. 29. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code stored in code storage means, said object code being generated by a data processing apparatus according to claim 1. 30. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by a data processing apparatus according to claim 1. 31. A data processing system comprising: a data processing apparatus according to claim 1; and a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by said data processing apparatus. 32. A data processing apparatus for generating a Control Data Flow Graph (CDFG), from a source code, of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said data processing apparatus comprising: condition storage means for registering, in advance, limiting conditions representing at least a physical structure and physical characteristics of said parallel operation apparatus; source input means for entering said source code; graph generating means for analyzing the language of said source code entered by said source input means and generating a Data Flow Graph (DFG); and schedule generating means for generating a CDFG in which operation states sequentially transited in a plurality of stages are scheduled, from the DFG generated by said graph generating means according to said limiting conditions. 33. A data processing apparatus according to claim 32, wherein said condition storage means comprises means for registering, as said limiting conditions, a predetermined threshold value corresponding to at least a number of said processing circuits; said graph generating means comprising means for generating said DFG in which a plurality of data processing are associated with each other based on a cause-and-effect relationship, from said source code; and said schedule generating means comprising means for scheduling data processing processes of said DFG in said operation states in a plurality of stages in a sequence corresponding to said cause-and-effect relationship, and shifting the operation states to a next stage each time a number of the scheduled data processing processes exceeds said predetermined threshold value. 34. A data processing apparatus according to claim 32, wherein said condition storage means comprises means for registering, as said limiting conditions, delay times of said processing circuits and said interconnection circuits and a time required by said operation cycles; said schedule generating means comprising means for scheduling the data processing of said DFG in said operation states in a plurality of stages in a sequence corresponding to a cause-and-effect relationship, and shifting the operation states to a next stage each time an accumulated value of said delay times of said processing circuits and said interconnection circuits used in the scheduled data processing exceeds said time required by operation cycles. 35. A data processing apparatus according to claim 32, further comprising: state detecting means for detecting a plurality of operation states to be assigned to one of the contexts from said operation states in a plurality of successively transited stages according to said limiting conditions; and state combining means for assigning the operation states detected by said state detecting means to one of said contexts. 36. A data processing apparatus for generating net lists of circuit resources from a Register Transfer Level (RTL) description of a parallel operation apparatus having a matrix of processing circuits each having a plurality of types of circuit resources for which processing data have different bit numbers, for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said data processing apparatus comprising: condition storage means for registering, in advance, limiting conditions representing at least a physical structure and physical characteristics of said parallel operation apparatus; description input means for entering the RTL description of said parallel operation apparatus; list generating means for generating net lists of the plurality of types of circuit resources from said RTL description entered by said description input means according to said limiting conditions; and list output means for outputting said net lists generated by said list generating means. 37. A data processing apparatus according to claim 36, wherein said parallel operation apparatus comprises a matrix circuit having said matrix of processing circuits and interconnection circuits, and a state manager, separate from said matrix circuit, for sequentially switching contexts of said matrix circuit in operation cycles, respectively, data processing apparatus further comprising: object storage means for registering, in advance, various object codes of said state manager which correspond to the operation states in a plurality of stages; state converting means for converting the RTL description of said state manager generated by a description generating means into corresponding object codes according to the net lists of said matrix circuit which have been generated by said list generating means; and object output means for outputting the object codes of said state manager which have been converted by said state converting means. 38. A data processing apparatus according to claim 36, wherein each of said processing circuits of said parallel operation apparatus comprises mb circuit resources for which processing data comprises mb(m-(bit)) data where "m" represents a natural number of "2" or greater and nb circuit resources for which processing data comprises nb(n-(bit)) data where "n" represents a natural number smaller than "m"; and said list generating means comprising means for generating net lists of m/nb circuit resources of said processing circuits from said RTL description according to said limiting conditions. 39. A data processing apparatus according to claim 36, further comprising: object storage means which comprises means for registering, in advance, various object codes of said processing circuits; processing layout means for assigning said net lists generated by said list generating means to said processing circuits of a matrix circuit in respective contexts in a plurality of cycles according to said limiting conditions; and code converting means for converting the net lists assigned to said processing circuits by said processing layout means into corresponding object codes. 40. A data processing apparatus according to claim 36, further comprising: state detecting means for detecting a plurality of operation states to be assigned to one of the contexts from said operation states in a plurality of successively transited stages according to said limiting conditions; and state combining means for assigning the operation states detected by said state detecting means to one of said contexts. 41. A data processing apparatus for generating object codes in respective contexts in a plurality of sequentially switched cycles from net lists of a matrix circuit of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said data processing apparatus comprising: condition storage means for registering, in advance, limiting conditions representing at least a physical structure and physical characteristics of said parallel operation apparatus; object storage means for registering, in advance, the object codes of said processing circuits; processing layout means for assigning said net lists to said processing circuits of said matrix circuit in the respective contexts in a plurality of cycles according to said limiting conditions; code converting means for converting the net lists assigned to said processing circuits by said processing layout means into corresponding object codes; and object output means for outputting the object codes of said processing circuits which have been converted by said code converting means. 42. A data processing apparatus according to claim 41, said object storage means comprises means for registering, in advance, various object codes of said interconnection circuits, further comprising: interconnection converting means for converting said net lists of said interconnection circuits into object codes according to the object codes of said processing circuits which have been converted by said code converting means. 43. A data processing apparatus according to claim 41, further comprising: state detecting means for detecting a plurality of operation states to be assigned to one of the contexts from said operation states in a plurality of successively transited stages according to said limiting conditions; and state combining means for assigning the operation states detected by said state detecting means to one of said contexts. 44. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code stored in code storage means, said object code being generated by a data processing apparatus according to claim 41. 45. A parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by a data processing apparatus according to claim 41. 46. A data processing system comprising: a data processing apparatus according to claim 41; and a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, said parallel operation apparatus being operable according to an object code entered from an external source into an object input means, said object code being generated by said data processing apparatus. 47. A method of processing data in a data processing apparatus for generating an object code from a source code descriptive of operation of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said object code containing at least contexts composed of said individually established operation instructions for sequentially switched operation cycles of said processing circuits and said interconnection circuits, said method comprising the steps of: receiving an entry of said source code; detecting operation states in successively transited stages corresponding to said contexts in the sequentially switched operation cycles from said source code according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus, and generating said object code; and outputting the generated object code. 48. A method of processing data in a data processing apparatus for generating a Control Data Flow Graph (CDFG), from a source code, of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said method comprising the steps of: entering said source code; analyzing a language of said source code which is entered and generating a Data Flow Graph (DFG); and generating a CDFG in which operation states in a plurality of stages are scheduled, from the DFG which has been generated according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus. 49. A method of processing data in a data processing apparatus for generating net lists of circuit resources from a Register Transfer Level (RTL) description of a parallel operation apparatus having a matrix of processing circuits each having a plurality of types of circuit resources for which processing data have different bit numbers, for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said method comprising the steps of: entering the RTL description of said parallel operation apparatus; generating net lists of the plurality of types of circuit resources from said RTL description according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus; and outputting said net lists which have been generated. 50. A method of processing data in a data processing apparatus for generating object codes in respective contexts in a plurality of sequentially switched cycles from net lists of a matrix circuit of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said method comprising the steps of: assigning said net lists to said processing circuits of said matrix circuit in the respective contexts in a plurality of cycles according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus; selectively converting the net lists assigned to said processing circuits into various object codes which have been registered in advance; and outputting the object codes of said processing circuits which have been converted. 51. A data processing apparatus including a computer program for a data processing apparatus for generating an object code from a source code descriptive of operation of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said object code containing at least contexts composed of said individually established operation instructions for sequentially switched operation cycles of said processing circuits and said interconnection circuits, said computer program enabling said data processing apparatus to carry out a process comprising the steps of: receiving an entry of said source code; detecting operation states in sequentially transited stages corresponding to said contexts in the sequentially switched operation cycles from said source code according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus, and generating said object code; and outputting the generated object code. 52. A data processing apparatus including an information storage medium storing a computer program according to claim 51. 53. A data processing apparatus including a computer program for a data processing apparatus for generating a Control Data Flow Graph (CDFG), from a source code, of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said computer program enabling said data processing apparatus to carry out a process comprising the steps of: entering said source code; analyzing a language of said source code which is entered and generating a Data Flow Graph (DFG); and generating a CDFG in which operation states in a plurality of stages are scheduled, from the DFG which has been generated according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus. 54. A data processing apparatus including an information storage medium storing a computer program according to claim 53. 55. A data processing apparatus including a computer program for a data processing apparatus for generating net lists of circuit resources from a Register Transfer Level (RTL) description of a parallel operation apparatus having a matrix of processing circuits each having a plurality of types of circuit resources for which processing data have different bit numbers, for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said computer program enabling said data processing apparatus to carry out a process comprising the steps of: entering the RTL description of said parallel operation apparatus; generating net lists of the plurality of types of circuit resources from said RTL description according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus; and outputting said net lists which have been generated. 56. A data processing apparatus including an information storage medium storing a computer program according to claim 55. 57. A data processing apparatus including a computer program for a data processing apparatus for generating object codes in respective contexts in a plurality of sequentially switched cycles from net lists of a matrix circuit of a parallel operation apparatus having a matrix of processing circuits for individually carrying out data processing according to individually established operation instructions, and interconnection circuits for individually switching connections between said processing circuits according to individually established operation instructions, said computer program enabling said data processing apparatus to carry out a process comprising the steps of: assigning said net lists to said processing circuits of said matrix circuit in the respective contexts in a plurality of cycles according to limiting conditions, registered in advance, representing at least a physical structure and physical characteristics of said parallel operation apparatus; selectively converting the net lists assigned to said processing circuits into various object codes which have been registered in advance; and outputting the object codes of said processing circuits which have been converted. 58. A data processing apparatus including an information storage medium storing a computer program according to claim 57. 59. A data processing system comprising: a parallel operation apparatus comprising a matrix circuit having a matrix of processing circuits and interconnection circuits, and a state manager, separate from said matrix circuit, for sequentially switching operation instructions for said matrix circuit sequentially in respective operation cycles; and a data processing apparatus for generating an object code separately for a data path and a finite-state machine from a source code descriptive of operation of said parallel operation apparatus; said matrix circuit corresponding to said data path, and said state manager corresponding to said finite-state machine.