[특허]Method for packaging chip and package assembly produced thereby

[미국특허] Method for packaging chip and package assembly produced thereby 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/50 H01L-021/02
출원번호	US-0995492 (2004-11-24)
우선권정보	TW-93127579 A(2004-09-10)
발명자 / 주소	Tiao,Kuo Tung
출원인 / 주소	Aiptek International, Inc.
대리인 / 주소	Troxell Law Office, PLLC
인용정보	피인용 횟수 : 21 인용 특허 : 12

초록 ▼

A chip package assembly is produced by preparing a transparent substrate in advance, a chip is electrically connected to a circuit layout of the transparent substrate. Make sure an unoccupied layer is sealed between the transparent substrate and the chip, so as to form the chip package assembly. After the processes mentioned above are done, the chip package assembly can leave the clean room to run post-processes, such as die sawing, or camera module packaging.

대표청구항 ▼

What is claimed is: 1. A method for packaging a chip, comprising the steps: preparing a transparent substrate; planting a circuit layout on a predetermined region of a first surface of the transparent substrate; providing a chip; arranging a joint pad between the circuit layout of the transparent substrate and the chip; connecting the chip to the circuit layout of the transparent substrate via the joint pad; arranging an electromagnetic wave reflection layer on a second surface of the transparent substrate; wherein the second surface is opposite to the first surface of the transparent substrate, and the electromagnetic wave reflection layer reflects a predetermined wave spectrum of the electromagnetic wave. 2. The method as claimed in claim 1, wherein the step of the joint pad arrangement further includes the steps: arranging the joint pad around the chip in a discontinuous manner; and coating a sealing paste around the joint pad; wherein the sealing paste connects the joint pad, the chip and the transparent substrate simultaneously, so as to form an unoccupied layer between the chip and the transparent substrate. 3. The method as claimed in claim 2, wherein the unoccupied layer is formed by a step: pumping into vacuum; being full of air naturally; or pouring an inert gas between the chip and the transparent substrate. 4. The method as claimed in claim 2, wherein the joint pad is made from a conductive material, such as a golden bump, or an anisotropic conductive film and paste (ADF). 5. The method as claimed in claim 1, wherein the step of the joint pad arrangement further includes the steps: circling the joint pad around the chip in a continuous manner in order to form an unoccupied layer between the chip and the transparent substrate. 6. The method as claimed in claim 5, wherein the unoccupied layer is formed by a step: pumping into vacuum; being full of air naturally; or pouring an inert gas between the chip and the transparent substrate. 7. The method as claimed in claim 5, wherein the joint pad is made of a conductive material and an insulative material in an alternate manner. 8. The method as claimed in claim 7, wherein the conductive material is made from a golden bump, or an anisotropic conductive film and paste (ADF). 9. The method as claimed in claim 1, wherein the joint pad is made on the chip or on the circuit layout of the transparent substrate in advance. 10. The method as claimed in claim 1, wherein the transparent substrate is made of optical glass or quartz. 11. The method as claimed in claim 1, wherein the step of the electromagnetic wave reflection layer arrangement further includes a step: sputtering an infrared ray filtering film on the second surface of the transparent substrate. 12. The method as claimed in claim 1, wherein the chip has a micro-lens array disposed on a surface thereof to face the first surface of the transparent substrate. 13. The method as claimed in claim 12, wherein the chip is an optical sensor with a pixel array, which corresponds to the micro-lens array; or the chip is composed of a plurality of LEDs (Light Emission Diode) arranged to correspond to the micro-lens array one on one.

이 특허에 인용된 특허 (12) 인용/피인용 타임라인 분석

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Kinsman, Larry D., Bumped die and wire bonded board-on-chip package.
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Hembree, David R., Chip on board and heat sink attachment methods.
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Hembree, David R., Chip on board and heat sink attachment methods.
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Fumihira, Ryuujin, Chip scale package in which layout of wiring lines is improved.
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Kinsman, Larry D., Flip-chip image sensor packages and methods of fabrication.
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Jiang, Tongbi, Method of fabricating tape attachment chip-on-board assemblies.
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Tong, Ho-Ming; Lee, Chun-Chi; Fang, Jen-Kuang; Huang, Min-Lung; Chen, Jau-Shoung; Su, Ching-Huei; Weng, Chao-Fu; Lee, Yung-Chi; Chou, Yu-Chen, Solder ball fabricating process.
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Tong, Ho-Ming; Lee, Chun-Chi; Fang, Jen-Kuang; Huang, Min-Lung; Chen, Jau-Shoung; Su, Ching-Huei; Weng, Chao-Fu; Lee, Yung-Chi; Chou, Yu-Chen, Solder ball fabrication process.
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Jun Andoh JP; Yoshihiro Morii JP; Toshio Kobayashi JP; Akio Yashiba JP; Hiroshi Takemoto JP; Takeshi Sano JP; Tsutomu Sakatsu JP, Solid-state imaging device and method of production of the same.
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이 특허를 인용한 특허 (21) 인용/피인용 타임라인 분석

Tischler, Michael A.; Schick, Philippe M.; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael A.; Schick, Philippe M.; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael A.; Schick, Philippe M.; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael A.; Schick, Philippe M.; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael A.; Schick, Philippe; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael; Schick, Philippe; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael; Schick, Philippe; Ashdown, Ian; Sheen, Calvin Wade; Jungwirth, Paul, Electronic devices with yielding substrates.
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Tischler, Michael A.; Schick, Philippe M.; Jungwirth, Paul; Sheen, Calvin Wade, Failure mitigation in arrays of light-emitting devices.
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Tischler, Michael A.; Schick, Philippe M.; Jungwirth, Paul; Sheen, Calvin Wade, Failure mitigation in arrays of light-emitting devices.
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Tischler, Michael; Schick, Philippe; Sheen, Calvin Wade; Jungwirth, Paul, Failure mitigation in arrays of light-emitting devices.
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Tischler, Michael Albert; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDS and LED lamps.
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Tischler, Michael A.; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael A.; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael A.; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael A.; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael A.; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael Albert; Odnoblyudov, Vladimir; Keogh, David, High efficiency LEDs and LED lamps.
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Tischler, Michael A.; Pinnington, Tom; Schick, Philippe M.; Jungwirth, Paul, Light-emitting element repair in array-based lighting devices.
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Tischler, Michael A., Methods of fabricating wafer-level flip chip device packages.
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Tischler, Michael A., Methods of fabricating wafer-level flip chip device packages.
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Tischler, Michael A., Wafer-level flip chip device packages and related methods.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Method for packaging chip and package assembly produced thereby 원문보기