초록 ▼

A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also has a first g

A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also has a first guard ring structure surrounding a portion of the active mask region to isolate the active region from an outer region of the mask substrate and a second guard ring structure having at least one fuse structure surrounding a portion of the first guard ring structure. The fuse structure is operably coupled to the active region to absorb a current from static electricity. The static electricity is accumulated by the active region to the pre-determined level and being discharged as current to the fuse structure while maintaining the active region free from damage from the static electricity.

대표청구항 ▼

What is claimed is: 1. A method for manufacturing integrated circuit devices using a mask, the method comprising: receiving a mask in a first pod, the mask including an active region and a guard ring structure having at least one fuse structure, the fuse structure including a plurality of elongated

What is claimed is: 1. A method for manufacturing integrated circuit devices using a mask, the method comprising: receiving a mask in a first pod, the mask including an active region and a guard ring structure having at least one fuse structure, the fuse structure including a plurality of elongated members; transferring the mask from the first pod into a second pod within a clean room environment; handling the mask in the clean room environment; accumulating static electricity on the mask during the handling in the clean room environment; discharging a portion of the static charge to the fuse on the guard ring structure of the mask while maintaining the active region of the mask free from static energy damage; and using the mask in an operation for manufacture of semiconductor integrated circuits. 2. The method of claim 1 wherein the operation is a lithography process. 3. The method of claim 1 wherein the static energy is characterized by a voltage of 1000 volts. 4. The method of claim 1 wherein the static energy is characterized by a voltage of greater than 3000 volts. 5. The method of claim 1 wherein each of the elongated members is a finger including a free end facing an insulating region. 6. The method of claim 5 wherein a small gap is defined between the free end and a conductive structure. 7. The method of claim 5 wherein the conductive structure is a region where electrostatic charge is accumulated. 8. The method of claim 6 wherein charge traverses from the conductive structure through the small gap to the finger. 9. The method of claim 8 wherein the finger acts as an antenna and once the charge traverses through the small gap, electrostatic charge is discharged. 10. A method for manufacturing integrated circuit devices using a mask, the method comprising: receiving a mask in a first pod, the mask including an active region and an anti-static guard ring structure, the guard ring structure further including a first guard ring structure and a second guard ring structure having a plurality of fuse structures; transferring the mask from the first pod into a second pod within a clean room environment; handling the mask in the clean room environment; discharging electrostatic charges built up from the handling of the mask to the plurality of fuse structures of the mask while maintaining the active region of the mask free from damage caused by electrostatic charges; and using the mask in an operation for manufacture of semiconductor integrated circuits. 11. The method of claim 10 wherein the first guard ring structure serves as isolation between the active region and the second guard ring structure. 12. The method of claim 10 wherein the first guard ring structure comprises a trench region filled with a dielectric layer. 13. The method of claim 12 wherein the trench region is 20 micron or less in width and 300 nm to 1000 nm in thickness. 14. The method of claim 10 wherein the second guard ring structure surrounds the periphery of the active region and the first guard ring structure. 15. The method of claim 10 wherein the second guard ring structure includes a plurality of fuse structures configured to form the guard ring structure in a sequential manner. 16. The method of claim 15 wherein each of the fuse structures includes a plurality of elongated members. 17. The method of claim 16 wherein each of the elongated members is a finger having a free end. 18. The method of claim 17 wherein each of the elongated members is substantially in parallel with another elongated member.