Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set.
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.
대표청구항▼
We claim: 1. A configurable integrated circuit (IC) having: a plurality of wiring layers; a first via programmed interconnect circuit having a first set of input terminals and a set of output terminals, wherein the interconnect circuit has several connection schemes for connecting the first input s
We claim: 1. A configurable integrated circuit (IC) having: a plurality of wiring layers; a first via programmed interconnect circuit having a first set of input terminals and a set of output terminals, wherein the interconnect circuit has several connection schemes for connecting the first input set to the output set; the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets; a second set of input terminals for carrying a set of input signals, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set; and a plurality of vias each for connecting an input terminal in the first set with an input terminal in the second set; wherein during the design of the IC, the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the first via programmed interconnect circuit implementing the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set; wherein the interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes. 2. The integrated circuit of claim 1 further comprising a signal generator that generates the control signal. 3. The integrated circuit of claim 1, wherein all input terminals in the first and second sets overlap at the same angle. 4. The integrated circuit of claim 3, wherein the angle is 90째. 5. The integrated circuit of claim 3, wherein all input terminals in the first set are on a different wiring layer than all input terminals in the second set. 6. The integrated circuit of claim 1, wherein the interconnect circuit is a decoder. 7. The integrated circuit of claim 1, wherein the interconnect circuit is a multiplexer. 8. The integrated circuit of claim 1, wherein the first via programmed interconnect circuit is one of a plurality of via programmed interconnect circuits of the IC, wherein the plurality of via programmed interconnect circuits are arranged in an array having multiple rows and columns, wherein each particular via programmed interconnect circuit in the set has: a first set of input terminals and a set of output terminals, wherein the particular interconnect circuit has several connection schemes for connecting the first input set to the output set; wherein the particular via programmed interconnect circuit operating equivalently to another configurable interconnect circuit that performs different interconnect operations based on different configuration data sets; a second set of input terminals for carrying a set of input signals, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set; and a plurality of vias each for connecting an input terminal in the first set with an input terminal in the second set; wherein during the design of the IC the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the particular via programmed interconnect circuit implementing the equivalent operation of the other configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set; wherein the particular interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes. 9. The integrated circuit of claim 1 further comprising a set of logic circuits configurably connected by the interconnect circuits, wherein each logic circuit is for performing a set of functions. 10. A configurable integrated circuit (IC) having a plurality of wiring layers, said IC comprising: a) a first via programmed interconnect circuit for connecting an input data set to an output data set, said first via programmed interconnect circuit having a first set of inputs, the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets; b) a second set of inputs for providing the input data set, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set; c) a plurality of vias defined between certain inputs in the first set and certain inputs in the second set, wherein during the design of the IC, the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the first via programmed interconnect circuit implementing the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set, and d) a signal generator for supplying a control signal to the first via programmed interconnect circuit, which then connects the input data set to the output data set in a particular manner. 11. The integrated circuit of claim 10, wherein all inputs in the first and second sets overlap at the same angle. 12. The integrated circuit of claim 11, wherein the angle is 90째. 13. The integrated circuit of claim 11, wherein all inputs in the first set are on a different wiring layer than all inputs in the second set. 14. A method of specifying a first via programmed interconnect circuit in a integrated circuit with a plurality of wiring layers, the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets, the method comprising: a) defining a first set of input terminals and a set of output terminals for the first via programmed interconnect circuit; b) defining a second set of input terminals for carrying a set of input signals, wherein at least a plurality of the second set of input terminals are on a different wiring layer than at least a plurality of the first set of input terminals; c) from a group of potential vias between the first and second set of input terminals, defining a plurality of vias between certain input terminals in the first and second sets, such that the first via programmed interconnect circuit implements the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set; and d) supplying a control signal to the first via programmed interconnect circuit to enable the first via programmed interconnect circuit to connect the first input terminal set to the output terminal set by using a particular one of a plurality of connection schemes that the first via programmed interconnect circuit can use to connect the first input terminal set to the output terminal set. 15. The method of claim 14 further comprising defining the set of potential via sites between the first input terminal set and the second input terminal set, wherein defining the set of vias comprises selecting certain potential via sites to place vias in order to embed configuration data in the set of vias. 16. The method of claim 15, wherein the potential via sites are arranged as a two-dimensional array of potential sites. 17. The method circuit of claim 14, wherein all inputs in the first and second sets of inputs overlap at the same angle. 18. The method of claim 17, wherein the angle is 90째. 19. The method of claim 17, wherein all inputs in the first set are on a different wiring layer than all inputs in the second set.
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Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
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Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
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