[특허]Selectable real time sample triggering for a plurality of inputs of an analog-to-digital converter

Microchip Technology Inc.

검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
검색연산자

검색도움말
검색연산자	기능	검색시 예
()	우선순위가 가장 높은 연산자	예1) (나노 (기계 \| machine))
공백	두 개의 검색어(식)을 모두 포함하고 있는 문서 검색	예1) (나노 기계) 예2) 나노 장영실
\|	두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색	예1) (줄기세포 \| 면역) 예2) 줄기세포 \| 장영실
!	NOT 이후에 있는 검색어가 포함된 문서는 제외	예1) (황금 !백금) 예2) !image
*	검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색	예) semi*
""	따옴표 내의 구문과 완전히 일치하는 문서만 검색	예) "Transform and Quantization"

과학기술 지식인프라 ScienceON

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

MyON담기

내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Selectable real time sample triggering for a plurality of inputs of an analog-to-digital converter

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03M-001/00
미국특허분류(USC)	341/141; 341/155
출원번호	US-0236371 (2005-09-27)
발명자 / 주소	Kris,Bryan
출원인 / 주소	Microchip Technology Inc.
대리인 / 주소	Baker Botts L.L.P.
인용정보	피인용 횟수 : 19 인용 특허 : 2

초록
▼

An analog-to-digital conversion apparatus for converting a plurality of analog input signals may include a plurality of analog input, a plurality of sample and hold circuits, one or more analog-to-digital converters (ADCs), a plurality of trigger selection circuits, and one or more analog multiplexers. The analog inputs may receive an analog input signals. The sample and hold circuits may include an input selectively coupled to at least one of the plurality of input and an output. The analog-to-digital converters (ADCs) may include an input and an output. The trigger selection circuits may selectively couple one of the inputs to one of the sample and hold circuits. The analog multiplexers may include a plurality of inputs selectively coupled to one or more of the sample and hold circuit outputs and an output coupled to one of the one or more analog-to-digital-converters.

대표
청구항
▼

What is claimed is: 1. An analog-to-digital conversion apparatus for converting a plurality of analog input signals, comprising: a plurality of analog inputs, each to receive an analog input signal; a plurality of sample and hold circuits, each comprising an input selectively coupled to at least one of the plurality of inputs and an output; at least one analog-to-digital converter (ADCs), each comprising an input and an output; a plurality of trigger selection circuits, for selectively coupling selected ones of the plurality of analog inputs to a respective one of the sample and hold circuits; and at least one analog multiplexer, comprising a plurality of inputs, each for selectively coupling to at least one of the sample and hold circuit outputs and an output coupled to one of the at least one analog-to-digital-converters. 2. The analog-to-digital conversion apparatus of claim 1, where each of the trigger selection circuits comprise: a trigger multiplexer comprising a plurality of trigger inputs, each to receive a trigger signal, a control input to receive a trigger select signal, and an output; a trigger select control register coupled to the trigger multiplexer control input, wherein the register is operable to store a value to control which of the plurality of trigger signals are selected by the trigger multiplexer; an edge detector comprising an input coupled to the trigger multiplexer output and an output, where the edge detector produces a signal when a signal from the trigger multiplexer is asserted; and a sample request latch comprising a set input coupled to the edge detector output, an output to cause one of the plurality of sample and hold circuits to receive an analog input signal from one of the plurality of input, and a clear input. 3. The analog-to-digital conversion apparatus of claim 2, where each trigger selection circuit further comprises: a sample delay circuit comprising an input coupled to a sample request latch Q output and output coupled to the sample request latch clear input, wherein the sample delay circuit causes the sample request latch to clear a predetermine time after a sample request latch Q output is active. 4. The analog-to-digital conversion apparatus of claim 2, where each trigger selection circuit further comprises: a conversion request latch comprising a set input coupled to the sample request latch clear input, a Q output to signal that sample and hold register associated with the trigger selection circuit is ready for conversion, and a clear input to clear the conversion request latch. 5. The analog-to-digital conversion apparatus of claim 1, wherein each of the plurality of input is associated with one sample and hold circuit. 6. The analog-to-digital conversion apparatus of claim 1, wherein the plurality of inputs are grouped into pairs and wherein each pair of input is associated with one sample and hold circuit. 7. The analog-to-digital conversion apparatus of claim 1, further comprising: at least one request for conversion selection circuit, each to receive sample ready signals from the plurality of trigger select logic circuits and control at least one of the analog multiplexers. 8. The analog-to-digital conversion apparatus of claim 7, where at least one of the request for conversion selection circuits comprise: two or more sample ready multiplexers, each comprising at least one input coupled to one of the at least one sample and hold circuits, a control input, and an output; a priority encoder comprising a plurality of inputs coupled to the at least one sample ready multiplexer output, an address output, and a request for conversion output; a conversion request latch comprising an multiplexer ID input, a multiplexer ID output, and a clear input, where the conversion request latch is operable to store a multiplexer ID of a sample to be converted; and an address selection multiplexer to convert the multiplexer ID output of the request conversion latch to the address of the sample to converted. 9. The analog-to-digital conversion apparatus of claim 1, further comprising: one or more registers to store conversion results. 10. A pulse width modulation (PWM) control system for monitoring a plurality of analog input signals, comprising: a plurality of analog inputs, each to receive an analog input signal; a plurality of sample and hold circuits, each comprising an input selectively coupled to at least one of the plurality of input and an output; at least one analog-to-digital converter (ADCs), comprising an input and an output; a plurality of trigger selection circuits, for selectively coupling a selected one of the plurality of analog inputs to a corresponding one of the plurality of sample and hold circuits; and at least one analog multiplexer, comprising a plurality of inputs selectively coupled to one or more of the sample and hold circuit outputs and an output coupled to one of the one or more ADCs. 11. The PWM control system of claim 10, wherein each of the plurality of inputs is associated with one sample and hold circuit. 12. The PWM control system of claim 10, wherein the plurality of inputs are grouped into pairs and wherein each pair of inputs is associated with one sample and hold circuit. 13. The PWM control system of claim 10, further comprising: at least one request for conversion selection circuit, for receiving sample ready signals from the plurality of trigger select logic circuits and for controlling one or more of the analog multiplexers. 14. The PWM control system of claim 10, further comprising: one or more registers to store conversion results. 15. A method for converting a plurality of analog input signals to digital output signals, comprising: associating each of the plurality of analog input signals with at least one trigger signal; detecting if at least one trigger signal associated with one of the analog inputs is active and, if so: sending a sample request signal to a sample request latch; if a sample and hold circuit associated with the analog input signal is available, switching the analog input to the sample and hold circuit associated with the analog input signal to sample and hold the analog input associated with the one or more trigger signals; sending a sample ready signal to a request for conversion selection circuit; if an analog-to-digital converter is available, and the sample and hold circuit associated with the sampled analog input signal is the highest priority requester, sending the sampled analog input signal to the analog to digital converter; converting the sampled and held analog input signal to a digital value; and storing the digital value in a result register. 16. The method of claim 15, where sending a sample ready signal to a request for conversion selection circuit comprises: sending an address of the sampled analog input signal. 17. The method of claim 15, further comprising: storing the address of the sampled analog input signal while the sampled analog input signal is being converted to the digital value; and clearing the address of the sampled analog input signal after the sampled analog input signal is converted to the digital value. 18. The method of claim 15, further comprising: clearing the sample and hold circuit after the sampled analog input signal is sent to the analog-to-digital converter. 19. The method of claim 15, further comprising: outputting the digital value to a serial bus.

인용문헌 (2)

이 특허를 인용한 특허 (19)

IPC 상위 출원인

내보내기

상세정보
내보내기 구분	파일저장 인쇄 메일전송
구성항목	관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	> 총 건의 자료가 검색되었습니다. > 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) > 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. > 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) > 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오 > ~ > Text(ASCII format) Excel format

과학기술 지식인프라 ScienceON

ScienceON Chatbot

연합인증

특허 상세정보

Selectable real time sample triggering for a plurality of inputs of an analog-to-digital converter

초록
▼

대표
청구항
▼

인용문헌 (2)

이 특허를 인용한 특허 (19)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

ScienceON Chatbot

연합인증

특허 상세정보

Selectable real time sample triggering for a plurality of inputs of an analog-to-digital converter

초록 ▼

대표청구항 ▼

인용문헌 (2)

이 특허를 인용한 특허 (19)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

초록
▼

대표
청구항
▼