초록 ▼

An analog-to-digital conversion apparatus for converting a plurality of analog input signals may include a plurality of analog input, a plurality of sample and hold circuits, one or more analog-to-digital converters (ADCs), a plurality of trigger selection circuits, and one or more analog multiplexe

An analog-to-digital conversion apparatus for converting a plurality of analog input signals may include a plurality of analog input, a plurality of sample and hold circuits, one or more analog-to-digital converters (ADCs), a plurality of trigger selection circuits, and one or more analog multiplexers. The analog inputs may receive an analog input signals. The sample and hold circuits may include an input selectively coupled to at least one of the plurality of input and an output. The analog-to-digital converters (ADCs) may include an input and an output. The trigger selection circuits may selectively couple one of the inputs to one of the sample and hold circuits. The analog multiplexers may include a plurality of inputs selectively coupled to one or more of the sample and hold circuit outputs and an output coupled to one of the one or more analog-to-digital-converters.

대표청구항 ▼

What is claimed is: 1. An analog-to-digital conversion apparatus for converting a plurality of analog input signals, comprising: a plurality of analog inputs, each to receive an analog input signal; a plurality of sample and hold circuits, each comprising an input selectively coupled to at least on

What is claimed is: 1. An analog-to-digital conversion apparatus for converting a plurality of analog input signals, comprising: a plurality of analog inputs, each to receive an analog input signal; a plurality of sample and hold circuits, each comprising an input selectively coupled to at least one of the plurality of inputs and an output; at least one analog-to-digital converter (ADCs), each comprising an input and an output; a plurality of trigger selection circuits, for selectively coupling selected ones of the plurality of analog inputs to a respective one of the sample and hold circuits; and at least one analog multiplexer, comprising a plurality of inputs, each for selectively coupling to at least one of the sample and hold circuit outputs and an output coupled to one of the at least one analog-to-digital-converters. 2. The analog-to-digital conversion apparatus of claim 1, where each of the trigger selection circuits comprise: a trigger multiplexer comprising a plurality of trigger inputs, each to receive a trigger signal, a control input to receive a trigger select signal, and an output; a trigger select control register coupled to the trigger multiplexer control input, wherein the register is operable to store a value to control which of the plurality of trigger signals are selected by the trigger multiplexer; an edge detector comprising an input coupled to the trigger multiplexer output and an output, where the edge detector produces a signal when a signal from the trigger multiplexer is asserted; and a sample request latch comprising a set input coupled to the edge detector output, an output to cause one of the plurality of sample and hold circuits to receive an analog input signal from one of the plurality of input, and a clear input. 3. The analog-to-digital conversion apparatus of claim 2, where each trigger selection circuit further comprises: a sample delay circuit comprising an input coupled to a sample request latch Q output and output coupled to the sample request latch clear input, wherein the sample delay circuit causes the sample request latch to clear a predetermine time after a sample request latch Q output is active. 4. The analog-to-digital conversion apparatus of claim 2, where each trigger selection circuit further comprises: a conversion request latch comprising a set input coupled to the sample request latch clear input, a Q output to signal that sample and hold register associated with the trigger selection circuit is ready for conversion, and a clear input to clear the conversion request latch. 5. The analog-to-digital conversion apparatus of claim 1, wherein each of the plurality of input is associated with one sample and hold circuit. 6. The analog-to-digital conversion apparatus of claim 1, wherein the plurality of inputs are grouped into pairs and wherein each pair of input is associated with one sample and hold circuit. 7. The analog-to-digital conversion apparatus of claim 1, further comprising: at least one request for conversion selection circuit, each to receive sample ready signals from the plurality of trigger select logic circuits and control at least one of the analog multiplexers. 8. The analog-to-digital conversion apparatus of claim 7, where at least one of the request for conversion selection circuits comprise: two or more sample ready multiplexers, each comprising at least one input coupled to one of the at least one sample and hold circuits, a control input, and an output; a priority encoder comprising a plurality of inputs coupled to the at least one sample ready multiplexer output, an address output, and a request for conversion output; a conversion request latch comprising an multiplexer ID input, a multiplexer ID output, and a clear input, where the conversion request latch is operable to store a multiplexer ID of a sample to be converted; and an address selection multiplexer to convert the multiplexer ID output of the request conversion latch to the address of the sample to converted. 9. The analog-to-digital conversion apparatus of claim 1, further comprising: one or more registers to store conversion results. 10. A pulse width modulation (PWM) control system for monitoring a plurality of analog input signals, comprising: a plurality of analog inputs, each to receive an analog input signal; a plurality of sample and hold circuits, each comprising an input selectively coupled to at least one of the plurality of input and an output; at least one analog-to-digital converter (ADCs), comprising an input and an output; a plurality of trigger selection circuits, for selectively coupling a selected one of the plurality of analog inputs to a corresponding one of the plurality of sample and hold circuits; and at least one analog multiplexer, comprising a plurality of inputs selectively coupled to one or more of the sample and hold circuit outputs and an output coupled to one of the one or more ADCs. 11. The PWM control system of claim 10, wherein each of the plurality of inputs is associated with one sample and hold circuit. 12. The PWM control system of claim 10, wherein the plurality of inputs are grouped into pairs and wherein each pair of inputs is associated with one sample and hold circuit. 13. The PWM control system of claim 10, further comprising: at least one request for conversion selection circuit, for receiving sample ready signals from the plurality of trigger select logic circuits and for controlling one or more of the analog multiplexers. 14. The PWM control system of claim 10, further comprising: one or more registers to store conversion results. 15. A method for converting a plurality of analog input signals to digital output signals, comprising: associating each of the plurality of analog input signals with at least one trigger signal; detecting if at least one trigger signal associated with one of the analog inputs is active and, if so: sending a sample request signal to a sample request latch; if a sample and hold circuit associated with the analog input signal is available, switching the analog input to the sample and hold circuit associated with the analog input signal to sample and hold the analog input associated with the one or more trigger signals; sending a sample ready signal to a request for conversion selection circuit; if an analog-to-digital converter is available, and the sample and hold circuit associated with the sampled analog input signal is the highest priority requester, sending the sampled analog input signal to the analog to digital converter; converting the sampled and held analog input signal to a digital value; and storing the digital value in a result register. 16. The method of claim 15, where sending a sample ready signal to a request for conversion selection circuit comprises: sending an address of the sampled analog input signal. 17. The method of claim 15, further comprising: storing the address of the sampled analog input signal while the sampled analog input signal is being converted to the digital value; and clearing the address of the sampled analog input signal after the sampled analog input signal is converted to the digital value. 18. The method of claim 15, further comprising: clearing the sample and hold circuit after the sampled analog input signal is sent to the analog-to-digital converter. 19. The method of claim 15, further comprising: outputting the digital value to a serial bus.