초록 ▼

The variable start-up circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of

The variable start-up circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable start-up circuits provide an output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.

대표청구항 ▼

What is claimed is: 1. A variable start-up circuit for enabling the output voltage level to reach the equilibrium in switching regulator according to schedule, comprising: a feedback line connected with the output and input of the variable start-up circuit and also coupled to the load; a sensor for

What is claimed is: 1. A variable start-up circuit for enabling the output voltage level to reach the equilibrium in switching regulator according to schedule, comprising: a feedback line connected with the output and input of the variable start-up circuit and also coupled to the load; a sensor for sensing a voltage at the output, comparing with the midpoint voltage decided by the device aspect ratios of the sensing inverter, and providing its output; an N-bit binary-weighted triggering circuit array with the base triggering transistor for generating a total current corresponding to an N-bit digital input and an output of the sensor; a current mirror for receiving the total current and providing the total current to the output; and a current source coupled to the output. 2. The circuit as recited in claim 1 wherein the sensor is inverter. 3. The circuit as recited in claim 1 wherein the sensor is comparator. 4. The circuit as recited in claim 1 wherein the sensor is operational amplifier. 5. The circuit as recited in claim 1 wherein the sensor is CMOS NAND gate since the two-input CMOS NAND gate can be used as an enabling inverter with one input serving as an active high enable input and the other used as the logical input. 6. The circuit as recited in claim 1 wherein the sensor is CMOS NOR gate since the two-input CMOS NOR gate can be used as an enabling inverter with one input serving as an active low enable input and the other used as the logical input. 7. The circuit as recited in claim 1 wherein an odd number of CMOS sensing inverters control the gates of triggering NMOS transistors coupled to the PMOS transistor current mirror. 8. The circuit as recited in claim 1 wherein an odd number of CMOS sensing inverters control the gates of triggering PMOS transistors coupled to the NMOS transistor current mirror. 9. The circuit as recited in claim 1 wherein an even number of CMOS sensing inverters directly control the gate of NMOS transistor in current source if there are not additional NMOS transistor current mirror and N-bit triggering circuit array including triggering PMOS transistors which are coupled each other. 10. The circuit as recited in claim 1 wherein an even number of CMOS sensing inverters directly control the gate of PMOS transistor in current source if there are not additional PMOS current mirror and N-bit triggering circuit array including triggering NMOS transistors which are coupled each other. 11. The circuit as recited in claim 1 wherein capacitors are added to necessary nodes. 12. The circuit as recited in claim 1 wherein the current mirror is cascode current mirror. 13. The circuit as recited in claim 1 wherein the current mirror is the Wilson current mirror. 14. The circuit as recited in claim 1 wherein the current mirror is simple current mirror. 15. The circuit as recited in claim 1 wherein power-down inverter and power-down transistors are further added to turn off all transistors and CMOS gates so that no current flows into the circuit during power-down mode. 16. The circuit as recited in claim 1 wherein the output of the variable start-up circuit is coupled to a load connected between the output and ground. 17. The circuit as recited in claim 16 wherein the output of the variable start-up circuit is at ground to ensure that no current flows into the circuit when the power-down input is at the power supply. 18. The circuit as recited in claim 1 wherein the output of the variable start-up circuit is coupled to a load connected between the output and power supply. 19. The circuit as recited in claim 18 wherein the output of the variable start-up circuit is at power supply to ensure that no current flows into the circuit when the power-down input is at the power supply. 20. The circuit as recited in claim 1 wherein the variable start-up circuit is applied to all switching regulators without regard to architectures, topologies, and schematics.