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Multi-structured Si-fin 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/66
  • H01L-029/94
  • H01L-031/062
  • H01L-031/06
  • H01L-031/113
  • H01L-031/101
  • H01L-031/119
  • H01L-031/115
출원번호 US-0778147 (2004-02-17)
우선권정보 KR-10-2003-0056636(2003-08-14)
발명자 / 주소
  • Lee,Deok Hyung
  • Lee,Byeong Chan
  • Jung,In Soo
  • Son,Yong Hoon
  • Choi,Siyoung
  • Kim,Taek Jung
출원인 / 주소
  • Samsung Electronics Co., Ltd.
대리인 / 주소
    Harness, Dickey &
인용정보 피인용 횟수 : 73  인용 특허 : 5

초록

Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclo

대표청구항

What is claimed is: 1. A semiconductor device comprising: a substrate; a semiconductor fin extending generally upwardly from the substrate, wherein the semiconductor fin includes; an upper portion, the upper portion having a first thickness t1 and a substantially constant width w0; and a lower port

이 특허에 인용된 특허 (5)

  1. Bin Yu, Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology.
  2. Chenming Hu ; Tsu-Jae King ; Vivek Subramanian ; Leland Chang ; Xuejue Huang ; Yang-Kyu Choi ; Jakub Tadeusz Kedzierski ; Nick Lindert ; Jeffrey Bokor ; Wen-Chin Lee, Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture.
  3. Lee, Kang-yoon; Park, Jong-woo, Integrated circuit devices having active regions with expanded effective widths and methods of manufacturing same.
  4. Pham, Daniel T.; Barr, Alexander L.; Mathew, Leo; Nguyen, Bich-Yen; Vandooren, Anne M.; White, Ted R., Method for forming a double-gated semiconductor device.
  5. Chan, Bor-Wen; Wang, Yu-I; Hsu, Chen-Yuan; Tao, Hun-Jan, Multiple etch method for fabricating split gate field effect transistor (FET) device.

이 특허를 인용한 특허 (73)

  1. Cheng, Kangguo; Li, Juntao; Miao, Xin, Bulk fin STI formation.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  5. Chen, Kuang-Hsin; Tsao, Hsun-Chih; Lu, Jhi-Cherng; Hou, Chuan-Ping; Hsu, Peng-Fu; Chen, Hung-Wei; Lee, Di-Hong, FIN-FET device structure formed employing bulk semiconductor substrate.
  6. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chang, Chia-Wei; Liu, Chih-Fang; Peng, Chih-Tang; Huang, Tai-Chun; Chen, Ryan Chia-Jen, Fin profile structure and method of making same.
  17. Chang, Chia-Wei; Liu, Chih-Fang; Peng, Chih-Tang; Huang, Tai-Chun; Chen, Ryan Chia-Jen, Fin profile structure and method of making same.
  18. Wu, Xusheng; Chi, Min-hwa; Banghart, Edmund Kenneth, Fin structures and multi-Vt scheme based on tapered fin and method to form.
  19. Basker, Veeraraghavan S.; Gluschenkov, Oleg; Mochizuki, Shogo; Reznicek, Alexander, Gate top spacer for finFET.
  20. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  21. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  22. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  23. Wang, Chih-Jung; Chen, Tong-Yu, Method for fabricating MOS device.
  24. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  26. Jin, You-seung; Ahn, Jong-hyon, Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate.
  27. Mathew, Leo; Mora, Rode R., Method of making an inverted-T channel transistor.
  28. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  29. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  30. Liaw, Jhon Jhy, Multi-stage fin formation methods and structures thereof.
  31. Min, Byoung L.; Burnett, James D.; Mathew, Leo, Multiple device types including an inverted-T channel transistor and method therefor.
  32. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  33. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  38. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  39. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  40. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  41. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  42. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  43. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  44. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  45. Kwon, Byoung-Ho; Kim, Cheol; Kim, Ho-Young; Park, Se-Jung; Kim, Myeong-Cheol; Kang, Bo-Kyeong; Yoon, Bo-Un; Choi, Jae-Kwang; Choi, Si-Young; Jeong, Suk-Hoon; Seong, Geum-Jung; Jeong, Hee-Don; Choi, Yong-Joon; Han, Ji-Eun, Semiconductor device and method for fabricating the same.
  46. Kwon, Byoung-Ho; Kim, Cheol; Kim, Ho-Young; Park, Se-Jung; Kim, Myeong-Cheol; Kang, Bo-Kyeong; Yoon, Bo-Un; Choi, Jae-Kwang; Choi, Si-Young; Jeong, Suk-Hoon; Seong, Geum-Jung; Jeong, Hee-Don; Choi, Yong-Joon; Han, Ji-Eun, Semiconductor device and method for fabricating the same.
  47. Kwon, Byoung-Ho; Kim, Cheol; Kim, Ho-Young; Park, Se-Jung; Kim, Myeong-Cheol; Kang, Bo-Kyeong; Yoon, Bo-Un; Choi, Jae-Kwang; Choi, Si-Young; Jeong, Suk-Hoon; Seong, Geum-Jung; Jeong, Hee-Don; Choi, Yong-Joon; Han, Ji-Eun, Semiconductor device and method for fabricating the same.
  48. Kim, Dong-Kwon; Lee, Yong-Woo, Semiconductor device and method of fabricating the same.
  49. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  50. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  51. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  52. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  53. Park, Byungjae; Shin, Heonjong; Cho, Hagju; Yeo, Kyounghwan, Semiconductor devices having a spacer on an isolation region.
  54. Chang, Chia-Wei; Chen, Ryan Chia-Jen; Thitinun, Srisuda, Semiconductor fin structures and methods for forming the same.
  55. Chang, Chia-Wei; Thitinun, Srisuda; Chen, Ryan Chia-Jen, Semiconductor fin structures and methods for forming the same.
  56. Anderson, Brent A.; Nowak, Edward J., Sloped finFET with methods of forming same.
  57. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  58. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  59. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  60. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  61. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  62. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  63. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk FINFET device.
  64. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  65. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  66. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  67. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  68. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  69. Cheng, Kangguo; Li, Juntao; Yeh, Chun-Chen, Stress memorization technique for strain coupling enhancement in bulk finFET device.
  70. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  71. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  72. Chung, Woo Young, Vertical transistor of semiconductor device and method for forming the same.
  73. Chung, Woo Young, Vertical transistor of semiconductor device and method for forming the same.
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