Common memory device and controlling method thereof
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03M-013/03
H03M-013/00
출원번호
US-0197730
(2002-07-19)
우선권정보
KR-2001-43464(2001-07-19)
발명자
/ 주소
Seo,Seung Wan
출원인 / 주소
LG Electronics Inc.
대리인 / 주소
Fleshner &
인용정보
피인용 횟수 :
9인용 특허 :
4
초록▼
A mobile terminal in a mobile communications system stores received data with less hardware and more power-efficient power requirements compared with conventional terminals. These advantages are achieved by using a single memory to store data decoded by a plurality of decoder units. More specificall
A mobile terminal in a mobile communications system stores received data with less hardware and more power-efficient power requirements compared with conventional terminals. These advantages are achieved by using a single memory to store data decoded by a plurality of decoder units. More specifically, the terminal performs the steps of selecting one of two decoders for decoding data, decoding data in the selected decoder, determining an address of a common memory connected to the two decoders based on information in the decoded data; and storing the decoded data in the address of the common memory. The first decoder may be a viterbi decoder and the second decoder may be a turbo decoder. The common memory addresses may be determined based on the values of predetermined bits of decoded data output from the decoders. By using a common memory for this purpose, the terminal is able to realize a smaller size than could previously be attained.
대표청구항▼
What is claimed is: 1. A common memory device, comprising: a first memory for storing received data; a plurality of decoders for decoding the data; a common memory which stores data generated from the decoders; a switch which connects the first memory to the decoders; a conversion unit which cont
What is claimed is: 1. A common memory device, comprising: a first memory for storing received data; a plurality of decoders for decoding the data; a common memory which stores data generated from the decoders; a switch which connects the first memory to the decoders; a conversion unit which controls assignment of addresses in the common memory so that the decoders and the common memory are matched with each other; and a central processing unit (CPU) which controls the switch and the conversion unit. 2. The device of claim 1, wherein the decoders include a viterbi decoder and a turbo decoder. 3. The device of claim 2, wherein the common memory stores a survival path or a log likelihood ratio (LLR) respectively generated by the viterbi decoder and the turbo decoder. 4. The device of the claim 2, wherein the common memory stores the data generated by the viterbi decoder, when the switch connects the first memory to the viterbi decoder. 5. The device of claim 4, wherein the viterbi decoder comprises a viterbi logical calculating unit. 6. The device of claim 2, wherein the common memory stores the data generated in the turbo decoder when the switch connects the first memory to the turbo decoder. 7. The device of claim 6, wherein the turbo decoder comprises a turbo logical calculating unit. 8. The device of claim 1, wherein the conversion unit comprises: an address converting module which converts addresses of the decoders and transmits the addresses to the common memory; a data converting module which divides data of the decoders for communication between the common memory and another memory; and a memory selection converting module which selects a part of an address which is higher or lower than a decoder address, and which outputs a selection signal corresponding to the address. 9. The device of claim 1, wherein the CPU transmits a decoding selection signal to the switch and to the conversion unit at the same time. 10. The device of claim 1, wherein the CPU transmits a data transmission signal to the memory when the conversion unit completes setting a common memory address assignment. 11. A method for controlling a common memory device, comprising: identifying a decoding order between at least a first decoder and a second decoder; selecting one of the first decoder and the second decoder based on the decoding order; setting an address assignment in a common memory based on the selected decoder so that the decoders and the common memory are matched with each other; decoding data in the selected decoder; and storing the decoded data in the common memory based on said address assignment. 12. The method of claim 11, wherein the decoding order is set according to a predetermined communications standard. 13. The method of claim 11, wherein the selecting step includes selecting one of the first decoder and second decoder based on a decoding selection signal output from a CPU. 14. The method of claim 11, further comprising: transmitting data to the selected decoder when the setting step is completed. 15. The device of claim 11, wherein the first decoder is a viterbi decoder, and wherein the common memory stores a survival path generated by the viterbi decoder. 16. The device of claim 15, further comprising: storing the data generated by the viterbi decoder when the viterbi decoder is selected. 17. The method of claim 11, wherein one of the first decoder and the second decoder is a turbo decoder, said method further comprising: transmitting a turbo decoding selection signal for selecting the turbo decoder to a switch and a conversion unit which performs said setting step. 18. The method of claim 17, wherein the conversion unit sets the common memory address assignment when the turbo decoding selection signal is received. 19. The method of claim 11, wherein one of the first decoder and second decoder is a turbo decoder, and wherein the common memory stores a log likelihood ratio (LLR) generated by the turbo decoder through an address conversion unit. 20. The method of claim 19, further comprising: storing data generated by the turbo decoder when the turbo decoder is selected. 21. A method for processing data, comprising: (a) selecting one of first and second decoders for decoding data; (b) decoding data in the selected decoder; (c) determining an address of a common memory connected to the two decoders based on information in said decoded data; and (d) storing the decoded data in the address of said common memory, wherein the first decoder is a viterbi decoder and the common memory includes a plurality of memory sectors, and wherein step (c) comprises: receiving a viterbi decoder address; and selecting one of the memory sections based on values of a predetermined number of bits of the viterbi decoder address, said predetermined number of bits being less than a total number of bits of the viterbi decoder address. 22. The method of claim 21, wherein the second decoder is a turbo decoder. 23. The method of claim 22, wherein when the turbo decoder is selected, step (c) includes: receiving a turbo decoder address; and setting the address of said common memory based on a predetermined number of bits of said turbo decoder address. 24. The method of claim 23, wherein step (d) includes storing an LLR in the address of said common memory. 25. The method of claim 21, wherein step (d) includes storing a survival path in the address of said common memory. 26. A system for processing data, comprising: a first decoder; a second decoder; a first processor which selects one of the two decoders for decoding data; and a second processor which determines an address of a common memory connected to the first and second decoders based on information decoded the selected decoder, wherein the common memory includes a plurality of memory sections, wherein the first decoder assigns the common memory into a first predetermined number of bits for data and a second predetermined number of bits for address, and wherein when the first processor selects the first decoder, the second processor transmits a portion of the second predetermined number of bits for the address to each memory section and transmits a selection signal to one of the memory sections based on the remaining bits not transmitted to the memory for the address. 27. The system of claim 26, wherein the first decoder is a viterbi decoder and the second decoder is a turbo decoder. 28. The system of claim 26, wherein when the first processor selects the turbo decoder, the second processor sets the address of said common memory based on a predetermined number of bits of a turbo decoder address. 29. A method for assigning addresses, comprising: receiving decoded data from one of first and second decoders; and determining an address of a common memory connected to the two decoders based on information in said decoded data, wherein the first and second decoders assign the common memory into a different number of bits for data and address, and wherein determining the address comprises: matching the number of address and data bits transmitted to the common memory by converting the address and data bits transmitted from the first and second decoders into a matched number of bits. 30. The method of claim 29, wherein a first decoder is a viterbi decoder and the second decoder is a turbo decoder. 31. The method of claim 30, wherein when viterbi decoder data is received, said determining step includes: obtaining a viterbi decoder address from the viterbi decoder data; and setting the address of said common memory based on values of a predetermined number of bits of said viterbi decoder address. 32. The method of claim 31, wherein the setting step includes: selecting one of a plurality of memory sections of said common memory based on the values of the predetermined number of bits of said viterbi decoder address. 33. The method of claim 30, wherein when turbo decoder data is received, said determining step includes: obtaining a viterbi decoder address from the viterbi decoder data; and setting the address of said common memory based on a predetermined number of bits of said turbo decoder address. 34. A memory assignment unit, comprising: a first module which receives decoded data from one of two decoders; and a second module which determines an address of a common memory connected to the two decoders based on information in said decoded data, wherein the second module sets the address of said common memory by selecting one of a plurality of memory sections of said common memory based on the values of the predetermined number of bits of said viterbi decoder address. 35. The unit of claim 34, wherein a first decoder is a viterbi decoder and the second decoder is a turbo decoder. 36. The unit of claim 35, wherein when viterbi decoder data is received, the second module sets the address of said common memory based on values of a predetermined number of bits of a viterbi decoder address. 37. The unit of claim 35, wherein when turbo decoder data is received, the second module sets the address of said common memory based on a predetermined number of bits of a turbo decoder address.
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이 특허에 인용된 특허 (4)
Diamondstein Marc S. (Allentown PA) Sam Homayoon (Wescosville PA) Thierbach Mark E. (South Whitehall Township ; Lehigh County PA), Digital processor and viterbi decoder having shared memory.
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