IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0940792
(2001-08-29)
|
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발명자
/ 주소 |
- Farrar,Paul A.
- Geusic,Joseph
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| 출원인 / 주소 |
|
| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
13 인용 특허 :
167 |
초록
▼
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.
대표청구항
▼
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. An integrated circuit substrate comprising at least one buried conductor pattern provided within a monocrystalline substrate such that said buried conductor pattern is below a top surface of said substr
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. An integrated circuit substrate comprising at least one buried conductor pattern provided within a monocrystalline substrate such that said buried conductor pattern is below a top surface of said substrate and said buried conductor pattern is completely surrounded by the same monocrystalline substrate material of a same conductivity type of said monocrystalline substrate, said at least one buried conductor pattern forming at least a part of an interconnect between devices, and a conductive path extending from said buried conductor pattern to said devices, wherein at least a portion of said conductive path extends below said top surface of said substrate. 2. The integrated circuit of claim 1, further comprising a second buried conductor pattern having a pipe-shaped pattern. 3. The integrated circuit of claim 1, further comprising a second buried conductor pattern having a plate-shaped pattern. 4. The integrated circuit of claim 1, wherein said at least one buried conductor pattern is formed of a material selected from the group consisting of copper, copper alloy, silver, silver alloy, gold, gold alloy, tungsten, tungsten alloy, aluminum and aluminum alloy. 5. The integrated circuit of claim 1, wherein said monocrystalline substrate is a silicon substrate. 6. The integrated circuit of claim 1, wherein said monocrystalline substrate is a germanium substrate. 7. The integrated circuit of claim 1, wherein said monocrystalline substrate is a silicon-on-insulator substrate. 8. The integrated circuit of claim 1, wherein said monocrystalline substrate is a silicon-on-nothing substrate. 9. A buried conductor pattern within a monocrystalline substrate, comprising: at least one empty-spaced pattern in said monocrystalline substrate formed by annealing said substrate containing at least one hole drilled therein; a conductive material filling said empty space pattern such that said conductive material is below a top surface of said monocrystalline substrate and forms a buried conductor pattern, said buried conductor pattern being completely surrounded by the same monocrystalline substrate material of a same conductivity type of said monocrystalline substrate, said buried conductor pattern forming at least a part of an interconnect between devices; and a conductive path connecting said buried conductor pattern with the exterior of said monocrystalline substrate, wherein at least a portion of said conductive path extends below said top surface of said substrate. 10. The buried conductor pattern of claim 9, wherein said empty-spaced pattern has a pipe-shaped configuration. 11. The buried conductor pattern of claim 9, wherein said empty-spaced pattern has a plate-shaped configuration. 12. The buried conductor pattern of claim 9, wherein said empty-spaced pattern has a sphere-shaped configuration. 13. A processor system comprising: a processor; and a circuit coupled to said processor, at least one of said circuit and processor comprising: a conductive structure comprising a monocrystalline substrate having at least one empty space pattern formed by annealing said monocrystalline substrate having at least one hole drilled therein; a conductive material filling said empty space pattern such that said conductive material is below a top surface of said monocrystalline substrate and said conductive structure is completely surrounded by the same monocrystalline substrate material of a same conductivity type of said monocrystalline substrate, said conductive structure forming at least a part of an interconnect between devices; and a conductive path extending from said conductive structure to said top surface of said monocrystalline substrate, wherein at least a portion of said conductive path extends below said top surface of said substrate. 14. The processor based system of claim 13, wherein said empty-spaced pattern has a pipe-shaped configuration. 15. The processor system of claim 13, wherein said empty-spaced pattern has a plate-shaped configuration. 16. The processor system of claim 13, wherein said empty-spaced pattern has a sphere-shaped configuration. 17. The processor system of claim 13, wherein said circuit is a memory circuit. 18. The processor system of claim 13, wherein said circuit is a DRAM memory circuit. 19. The processor system of claim 13, wherein said circuit and said processor are integrated on same circuit. 20. The processor system of claim 13, wherein said processor comprises said conductive structure. 21. The processor system of claim 13, wherein said circuit comprises said conductive structure. 22. An integrated circuit substrate comprising a plurality of buried conductor patterns provided within a monocrystalline substrate such that said buried conductor patterns are below a top surface of said substrate and said buried conductor patterns are completely surrounded by the same monocrystalline substrate material of said monocrystalline substrate, said buried conductor patterns forming at least a part of an interconnect between devices, and a conductive path extending from each of said buried conductor patterns, wherein at least a portion of said conductive path extends below said top surface of said substrate. 23. The integrated circuit of claim 22 wherein at least one of said plurality of buried conductor patterns has a pipe-shaped pattern. 24. The integrated circuit of claim 23 wherein at least one of said plurality of buried conductor patterns has a spherical pattern. 25. An integrated circuit substrate comprising first and second buried conductor patterns provided within a monocrystalline substrate such that said buried conductor patterns are below a top surface of said substrate and said buried conductor patterns are completely surrounded by the same monocrystalline material of a same conductivity type of said monocrystalline substrate, said first and second buried conductive patterns forming at least a part of first and second interconnects between devices, respectively, wherein said first buried conductor pattern is located below said second buried conductor pattern and relative to said surface of said monocrystalline substrate, and a first conductive path extending from said first buried conductor pattern and a second conductive path extending from said second buried conductor pattern, wherein at least a portion of said conductive paths extend below said top surface of said substrate. 26. The integrated circuit of claim 25, further comprising a third buried conductor pattern located below said first and second buried conductor patterns and relative to a surface of said monocrystalline substrate and a third conductive path extending from said third buried conductor pattern. 27. The integrated circuit of claim 26, wherein one of said buried conductor patterns has a pipe-shaped pattern. 28. The integrated circuit of claim 26, wherein one of said buried conductor patterns has a plate-shaped pattern. 29. The integrated circuit of claim 26, wherein one of said buried conductor patterns has a spherical pattern. 30. The integrated circuit of claim 26, wherein said buried conductor patterns are formed of a conductive material selected from the group consisting of copper, copper alloy, silver, silver alloy, gold, gold alloy, tungsten, tungsten alloy, aluminum and aluminum alloy.
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