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[미국특허] Memory device having an adjustable voltage swing setting 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-001/10
출원번호 US-0890972 (2004-07-14)
발명자 / 주소
  • Garrett, Jr.,Billy Wayne
  • Dillon, legal representative,Nancy David
  • Ching,Michael Tak Kei
  • Stonecypher,William F.
  • Chan,Andy Peng Pui
  • Griffin,Matthew M.
  • Dillon, deceased,John B.
출원인 / 주소
  • Rambus Inc.
대리인 / 주소
    Vierra Magen Marcus & DeNiro LLP
인용정보 피인용 횟수 : 1  인용 특허 : 55

초록

A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count

대표청구항

What is claimed is: 1. A method of operation in an integrated circuit memory device that includes an output driver, wherein the method comprises: storing a value in a register, wherein the value is representative of a voltage swing setting of the output driver; and adjusting the voltage swing setti

이 특허에 인용된 특허 (55) 인용/피인용 타임라인 분석

  1. Huizer Cornelis M. (Eindhoven NLX), Adaptive electronic buffer system having consistent operating characteristics.
  2. Sullivan Steven K. (Beaverton OR) Branson Christopher W. (Beaverton OR), Adjustable impedance driver network.
  3. Schenck Stephen R. (McKinney TX), Adjustable low noise output circuit responsive to environmental conditions.
  4. Keeth Brent, Adjustable output driver circuit having parallel pull-up and pull-down elements.
  5. Cooperman Michael (Framingham MA) Sieber Richard W. (Attleboro MA), Bidirectional digital signal transmission system.
  6. Shu Lee-Lean (Los Altos CA) Knorpp Kurt (San Carlos CA), Binary weighted reference circuit for a variable impedance output buffer.
  7. Hisanaga Tetsuo (Kanagawa JPX) Hatanaka Hiroshi (Kanagawa JPX), Bridge balancing circuit.
  8. Michel Thomas J. (Hialeah FL) Clarke Robert (Cooper City FL), Bridge-balancing system for measuring extremely low currents.
  9. Ota Yoshiyuki (Kanagawa JPX) Tomioka Ichiro (Kanagawa JPX) Murakami Eiji (Hyogo JPX), Buffer circuit for regulating driving current.
  10. Zasio John J. (Sunnyvale CA), CMOS Circuit using transmission line interconnections.
  11. Beier, Stefan, Circuit arrangement for controlling the action of an adjusting device, in particular for a patient chair.
  12. Evans William A. (Swansea GBX) Rowlands Stuart L. (Swansea GBX), Circuit for providing a controlled resistance.
  13. Kurtz Anthony D. (Englewood NJ), Compensated pressure transducer employing digital processing techniques.
  14. Garrett ; Jr. Billy Wayne ; Dillon ; deceased John B. ; Ching Michael Tak-Kei ; Stonecypher William F. ; Chan Andy Peng-Pui ; Griffin Matthew M., Current control technique.
  15. Cavaliere Joseph R. (Hopewell Junction NY) Smith ; III George E. (Wappingers Falls NY), Current switch logic circuit with controlled output signal levels.
  16. Korteling Aart G. (Eindhoven NLX), Current-sensing circuit for an IC power semiconductor device.
  17. Hansen Craig C. ; Robinson Timothy B. ; Corry Alan G., DRAM with high bandwidth interface that uses packets and arbitration.
  18. Trommler Craig S. (Romoland CA) Finefrock Mark D. (Riverside CA), Digital piezoresistive pressure transducer.
  19. Dunlop Alfred E. (Murray Hill NJ) Gabara Thaddeus J. (North Whitehall Township ; Lehigh County PA) Knauer Scott C. (Mountainside NJ), Digitally controlled element sizing.
  20. Tam Ambrose W. C. (Hong Lok Yuen Taipo HKX), Digitally controlled variable resistor.
  21. Gunning William F. (Los Altos Hills CA), Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines.
  22. Cooperman Michael (Framingham MA) Sieber Richard (Attleboro MA), Electrical circuitry providing compatibility between different logic levels.
  23. Horowitz Mark A. (Palo Alto CA) Gasbarro James A. (Mountain View CA) Leung Wingyu (Cupertino CA), Electrical current source circuitry for a bus.
  24. Tedrow Kerry D. (Orangevale CA) Keeney Stephen N. (Sunnyvale CA) Fazio Albert (Los Gatos CA) Atwood Gregory E. (San Jose CA) Javanifard Johnny (Sacramento CA) Wojciechowski Kenneth (Folsom CA), High precision voltage regulation circuit for programming multiple bit flash memory.
  25. Hesson James H. (Boise ID), High speed CMOS driver circuit.
  26. Roberts Allen W. (Union City CA) McFarland ; Jr. Harold L. (Santa Clara CA) Lau Harlan (Campbell CA), High speed data bus system.
  27. Usami Mitsuo (Ohme JPX), High speed logic circuit and semiconductor integrated circuit device including variable impedance to provide reduced pow.
  28. Yoon Sun-byeong,KRX, High-speed current setting systems and methods for integrated circuit output drivers.
  29. Marbot Roland (Versailles FRX) Le Bihan Jean-Claude (Montrouge FRX) Cofler Andrew (Paris FRX) Nezamzadeh-Moosavi Reza (Bois d\Arcy FRX), Impedance adaptation process and device for a transmitter and/or receiver, integrated circuit and transmission system.
  30. Kobayashi Mikio (Kawasaki JPX), Input/output port including auxiliary low-power transistors.
  31. Gabara Thaddeus J. (North Whitehall Township ; Lehigh County PA), Integrated circuit buffer with improved drive capability.
  32. Shoji Masakazu (Warren NJ), Integrated circuits which compensate for local conditions.
  33. Akamatsu Norio (9-3 ; 4-chome Sumiyoshi-cho Tokushima-shi JPX) Tsukao Toshiya (Nara JPX), Load current control-type logic circuit.
  34. Usami Mitsuo (Akishima JPX), Logic circuit including variable impedance means.
  35. David B. Gustavson ; David V. James ; Hans A. Wiggers ; Peter B. Gillingham CA; Cormac M. O'Connell CA; Bruce Millar CA; Jean Crepeau CA; Kevin J. Ryan ; Terry R. Lee ; Brent Keeth ; Troy A, Memory system having synchronous-link DRAM (SLDRAM) devices and controller.
  36. Eller Eldon E. (Seattle WA), Method and apparatus for calibrating resistance bridge-type transducers.
  37. Davis Paul Gregory ; Batra Pradeep ; Dillon John B. ; Krishnamohan Karnamadakala ; Gasbarro James A., Method and apparatus for setting a current of an output driver for the high speed bus.
  38. Gasparik Frank, Method and apparatus for transferring data on a voltage biased data line.
  39. Keller Hans W. (Winterthur CHX) Von Ritter Michael (Winterthur CHX), Method for temperature compensation and measuring circuit therefor.
  40. Takenaka Tsutomu (Tokyo JPX), Microprocessor system.
  41. Dillon John B. (Palo Alto CA) Nimmagadda Srinivas (Santa Clara CA) Moncayo Alfredo (Redwood City CA), Modular bus with single or double parallel termination.
  42. Kondoh Harufusa (Hyogo JPX) Uramoto Shinichi (Hyogo JPX), Output circuit for semiconductor integrated circuits having controllable load drive capability and operating method ther.
  43. Asano Michio (Tokorozawa JPX) Masaki Akira (Musashino JPX) Ishibashi Kenichi (Kokubunji JPX), Output circuit having transistor monitor for matching output impedance to load impedance.
  44. Branson Christopher W. (Hillsboro OR), Output device circuit and method to minimize impedance fluctuations during crossover.
  45. Stewart Roger G. (Neshanic Station NJ), Overload protection circuit for output driver.
  46. Suzuki Masayoshi (Hitachiota JPX) Horii Hidesato (Katsuta JPX), Power semiconductor device including an arrangement for controlling load current by independent control of a plurality o.
  47. Tanaka Hiroaki (Okazaki JPX) Enya Takeshi (Nishio JPX) Nakamura Katsumi (Okazaki JPX), Power source circuit and bridge type measuring device with output compensating circuit utilizing the same.
  48. Krechmery Roger L. (Riverside CA) Finefrock Mark D. (Riverside CA), Pressure transducer with integral digital temperature compensation.
  49. Patel Hitesh N. (8610 Causeway Houston TX 77083) Hohl Jakob H. (10249 E. Placita Cresta Feliz Tucson AZ 85749) Palusinski Olgierd A. (Dept. of ECE ; Univ. of Arizona Tucson AZ 85719), Self adjusting CMOS transmission line driver.
  50. Biber Alice I. (Needham MA) Stout Douglas W. (Milton VT), Self-adjusting impedance matching driver.
  51. Inaba Hideo (Tokyo JPX), Semiconductor integrated circuit provided with monitor-elements for checking affection of process deviation on other ele.
  52. Tanaka Yasunori (Yokohama JPX), Slew-rate limited output driver having reduced switching noise.
  53. King Philip N. (Ft. Collins CO), Switched drivers providing backmatch impedance for circuit test systems.
  54. Cox Dennis T. (Rochester MN) Guertin David L. (Rochester MN) Johnson Charles L. (Rochester MN) Rudolph Bruce G. (Rochester MN) Turner Mark E. (Colchester VT) Williams Robert R. (Rochester MN), VLSI performance compensation for off-chip drivers and clock generation.
  55. Michelsen Jeffery M. (Mesa AZ), Variable drive output buffer circuit.

이 특허를 인용한 특허 (1) 인용/피인용 타임라인 분석

  1. Kaestner, Clemens M., Overcoming limited common-mode range for USB systems.

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