Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/301
H01L-021/02
H01L-021/46
H01L-021/78
H01L-021/70
출원번호
US-0082372
(2002-02-25)
발명자
/ 주소
Connell,Michael E.
Jiang,Tongbi
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Trask Britt
인용정보
피인용 횟수 :
16인용 특허 :
282
초록▼
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serv
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhance marking method.
대표청구항▼
What is claimed is: 1. A method for producing nonwarped semiconductor die from a wafer of a semiconductive material forming a substrate, said wafer of semiconductive material having a front side having integrated circuits formed on said semiconductive material, a back side, and a front side passiva
What is claimed is: 1. A method for producing nonwarped semiconductor die from a wafer of a semiconductive material forming a substrate, said wafer of semiconductive material having a front side having integrated circuits formed on said semiconductive material, a back side, and a front side passivation layer on a portion of said wafer of semiconductor material causing a stress, said method comprising: reducing a cross-section of said nonwarped semiconductor die by thinning said semiconductive material from said back side of said substrate for said nonwarped semiconductor die; applying a stress-balancing layer to said wafer of semiconductor material substantially balancing said stress caused by said front side passivation layer; and singulating said wafer of semiconductor material into a plurality of semiconductor dice. 2. A method in accordance with claim 1, wherein said front side passivation layer comprises a layer applied in fabrication of said nonwarped semiconductor die. 3. A method in accordance with claim 1, wherein said front side passivation layer comprises a layer of passivation material. 4. A method in accordance with claim 1, wherein said thinning comprises grinding. 5. A method in accordance with claim 1, wherein said thinning comprises a chemical-mechanical method. 6. A method in accordance with claim 1, wherein said semiconductor die comprises an integrated circuit semiconductor die. 7. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer substantially covering said back side. 8. A method in accordance with claim 1, wherein said stress-balancing layer comprises a strip covering a selected portion of a row of semiconductor dice on said wafer of semiconductor material. 9. A method in accordance with claim 1, wherein said stress-balancing layer comprises a plurality of portions, each portion of said plurality covering a selected portion of said thinned nonwarped semiconductor die on said wafer of semiconductive material. 10. A method in accordance with claim 9, wherein said selected portion comprises a majority of said thinned nonwarped semiconductor die. 11. A method in accordance with claim 1, wherein said stress-balancing layer comprises a film. 12. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process. 13. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD. 14. A method in accordance with claim 1, wherein said stress-balancing layer comprises a layer applied to said thinned nonwarped semiconductor die by one of VPE, MBE, and CMOSE. 15. A method in accordance with claim 1, wherein said stress-balancing layer comprises a single homogeneous component. 16. A method in accordance with claim 15, wherein said stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer. 17. A method in accordance with claim 1, wherein said stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material. 18. A method in accordance with claim 17, wherein said reinforcing particles comprise inorganic particles. 19. A method in accordance with claim 17, wherein said reinforcing particles comprise one of a metal, an alloy, glass, and a combination thereof. 20. A method in accordance with claim 17, wherein said reinforcing particles comprise particles for providing reinforcement in the X-Y plane of said stress-balancing layer. 21. A method in accordance with claim 17, wherein said reinforcing particles comprise particles for providing reinforcement in the X, Y, and Z directions. 22. A method in accordance with claim 17, wherein said solid matrix material comprises one of silicon dioxide, silicon nitride, and an organic polymeric material. 23. A method in accordance with claim 1, wherein said nonwarped semiconductor die comprises one of a DIP, SIP, ZIP, PLCC, SOJ, SIMM, DIMM, LOC, QFP, SOP, TSOP, and a flip-chip. 24. A method in accordance with claim 1, wherein said stress-balancing layer comprises a material markable with indicia. 25. A method in accordance with claim 22, wherein said stress-balancing layer comprises a material markable by optical radiation energy. 26. A method in accordance with claim 22, wherein said stress-balancing layer comprises a polytetrafluoroethylene tape. 27. A method in accordance with claim 25, further comprising exposing a portion of said material markable with optical energy exposing at least a portion of said material markable to one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) or carbon dioxide laser. 28. A method for producing nonwarped semiconductor die from a wafer having a front side, a back side, and a front side layer on a portion of said wafer causing a stress, said method comprising: reducing a cross-section of said nonwarped semiconductor die by thinning said semiconductor die; applying a stress-balancing layer to said wafer; and applying a tape over said stress-balancing layer, said tape comprising a UV-penetrable polyvinyl chloride tape having an acrylic UV-sensitive adhesive disposed thereon; exposing a portion of said tape with optical energy exposing at least a portion of said tape to one of a Nd:YAG, Nd-YLP or carbon dioxide laser; and singulating said wafer into a plurality of semiconductor dice. 29. A method in accordance with claim 28, wherein said stress-balancing layer comprises a first sublayer having high rigidity in the X-direction and a second sub-layer having high rigidity in the Y-direction. 30. A method in accordance with claim 28, wherein said stress-balancing layer comprises a layer having a coefficient of thermal expansion substantially similar to a coefficient of thermal expansion of said front side layer. 31. A method in accordance with claim 28, further comprising applying a die-attach adhesive to at least a portion of a surface of said stress-balancing layer. 32. A method in accordance with claim 28, further comprising applying a temporary reinforcement layer over at least a portion of said front side layer prior to thinning said back side. 33. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer of a semiconductive material forming a substrate, said semiconductive wafer of said semiconductive material having a front side having integrated circuits formed on said semiconductive material, a back side, and a stress applied thereto by a front side passivation layer, said method comprising: reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning semiconductive material from said back side thereof; applying a rigid stress-balancing layer to a portion of said thinned back side for substantially balancing said stress of said front side passivation layer; and singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice. 34. A method in accordance with claim 33, wherein said front side passivation layer comprises a layer applied in a microcircuit fabrication step. 35. A method in accordance with claim 33, wherein said front side passivation layer comprises a layer of passivation material. 36. A method in accordance with claim 33, wherein said thinning comprises grinding by a grinding apparatus. 37. A method in accordance with claim 33, wherein said thinning comprises a chemical-physical method. 38. A method in accordance with claim 33, wherein said small Z-dimension nonwarped semiconductor die comprises an integrated circuit semiconductor die. 39. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer substantially covering said thinned back side. 40. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a strip covering a selected portion of a row of semiconductor dice on said semiconductor wafer. 41. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a plurality of discrete portions, each of said plurality of discrete portion covering a selected portion of said thinned back side of a die on said semicondutor wafer. 42. A method in accordance with claim 41, wherein said selected portion comprises a majority of said thinned die back side. 43. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a film. 44. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process. 45. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD. 46. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a layer applied to said thinned back side by one of VPE, MBE, and CMOSE. 47. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a single homogeneous component. 48. A method in accordance with claim 47, wherein said rigid stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer. 49. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material. 50. A method in accordance with claim 49, wherein said reinforcing particles comprise particles of inorganic material. 51. A method in accordance with claim 49, wherein said reinforcing particles comprise one of a metal, an alloy, and glass. 52. A method in accordance with claim 49, wherein said reinforcing particles comprise particles for providing reinforcement in the X-Y plane of said rigid stress-balancing layer. 53. A method in accordance with claim 49, wherein said reinforcing particles comprise particles for providing reinforcement in the X, Y, and Z directions. 54. A method in accordance with claim 49, wherein said solid matrix material comprises one of silicon dioxide, silicon nitride, and an organic polymeric material. 55. A method in accordance with claim 33, wherein said small Z-dimension nonwarped semiconductor die comprises one of a DIP, SIP, ZIP, PLCC, SOJ, SM, DIMM, LOC, QFP, SOP, TSOP, and a flip-chip. 56. A method in accordance with claim 33, wherein said rigid stress-balancing layer comprises a material markable with indicia. 57. A method in accordance with claim 56, wherein said rigid stress-balancing layer comprises a material markable by optical radiation energy. 58. A method in accordance with claim 56, wherein said rigid stress-balancing layer comprises a polytetrafluoroethylene tape. 59. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer having a front side, a back side, and a stress applied thereto by a front side layer, said method comprising: reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning said back side thereof; applying a rigid stress-balancing layer to a portion of said thinned back side, said rigid stress-balancing layer comprising a material markable with indicia; exposing a portion of said material markable with optical energy exposing at least a portion of said material markable to one of a Nd:YAG (yttrium aluminum garnet), Nd:YLP (pulsed yttrium fiber laser) or carbon dioxide laser; and singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice. 60. A method for producing a small Z-dimension nonwarped semiconductor die from a semiconductor wafer having a front side, a back side, and a stress applied thereto by a front side layer, said method comprising: reducing a cross-section of said small Z-dimension nonwarped semiconductor die by thinning said back side thereof; applying a rigid stress-balancing layer to a portion of said thinned back side; applying a tape over said rigid stress-balancing layer, said tape comprising a UV-penetrable polyvinyl chloride tape having an acrylic UV-sensitive adhesive disposed thereon; exposing a portion of said tape with optical energy exposing at least a portion of said tape to one of a Nd:YAG, Nd-YLP, or carbon dioxide laser; and singulating said semiconductor wafer into a plurality of nonwarped semiconductor dice. 61. A method in accordance with claim 60, wherein said rigid stress-balancing layer comprises a first sublayer having high rigidity in the X-direction, and a second sublayer having high rigidity in the Y-direction. 62. A method in accordance with claim 60, wherein said rigid stress-balancing layer comprises a layer having a coefficient of thermal expansion substantially similar to that of said front side layer. 63. A method in accordance with claim 60, further comprising applying a die-attach adhesive to at least a portion of an outer surface of said rigid stress-balancing layer. 64. A method in accordance with claim 60, further comprising applying a temporary reinforcement layer over said front side layer prior to thinning said back side. 65. A method for producing low Z-dimension nonwarped semiconductor dice having a die front side, a die back side, and a stress applied thereto by a die front side passivation layer, said method comprising: forming a semiconductor wafer of a semiconductive material, said semiconductive wafer of said semiconductive material having a front side, a back side, a plurality of microcircuits on said front side of said semiconductive material of said semiconductor wafer, and said die front side passivation layer applying stress to said semiconductor wafer; reducing a cross-section of said semiconductor wafer by thinning said back side of said semiconductive material of said semicondutor wafer; singulating said semiconductor wafer into a plurality of semiconductor dice; and applying a rigid stress-balancing layer to said thinned back side of said semiconductive material of said semiconductor wafer under conditions which apply a back side stress generally equivalent to said front side stress of said die front side passivation layer upon restoration to conditions of use of said low Z-dimension nonwarped semiconductor die. 66. A method in accordance with claim 65, wherein said die front side passivation layer comprises a layer of passivation material. 67. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of a chemical vapor deposition (CVD) process, an evaporation process, and an epitaxy process. 68. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of LPCVD, APCVD, MOCVD, PECVD, and UHVCVD. 69. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a layer applied to said back side by one of VPE, MBE, and CMOSE. 70. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a single homogeneous component. 71. A method in accordance with claim 70, wherein said rigid stress-balancing layer comprises one of a metal, alloy, metalorganic material, photoresist material, and an organic polymer. 72. A method in accordance with claim 65, wherein said rigid stress-balancing layer comprises a heterogeneous composite structure comprising reinforcing particles in a solid matrix material. 73. A method in accordance with claim 72, wherein said reinforcing particles comprises particles of inorganic material. 74. A method in accordance with claim 72, wherein said reinforcing particles comprise one of a metal, an alloy, and glass.
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