이 특허에 인용된 특허 (12) 인용/피인용 타임라인 분석

1. Takeuchi Koichiro (Akishima JPX) Kasahara Yukio (Machida JPX) Miura Akira (Akishima JPX) Iwaoka Hideto (Hachioji JPX) Sugiyama Tadashi (Mitaka JPX), Electro-optically controlled measurement probe system.

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2. Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX), Full wafer integrated circuit testing device.

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3. De Jong, Franciscus Gerardus Maria; Schuttert, Rodger Frank; De Wilde, Johannes, Integrated circuit with power supply test interface.

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4. Conner George W., Low cost, highly parallel memory tester.

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5. Gene E. Markozen, Method and apparatus for probing a conductor of an array of closely-spaced conductors.

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6. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.

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7. Eldridge, Benjamin N.; Grube, Gary W.; Mathieu, Gaetan L., Probe card assembly for contacting a device with raised contact elements.

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8. Benjamin N. Eldridge ; Gary W. Grube ; Gaetan L. Mathieu, Probe card for probing wafers with raised contact elements.

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9. Roach Steven D. (Colorado Springs CO), Probe with reduced input capacitance.

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10. Hiroshi Noda JP, Ringing preventive circuit, device under test board, pin electronics card, and semiconductor device.

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11. Schaeffer, Ralph; Crump, Brett, Selectively configurable microelectronic probes.

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12. Kie Y. Ahn ; Leonard Forbes, Silicon interposer with optical connections.

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이 특허를 인용한 특허 (37) 인용/피인용 타임라인 분석

1. Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.

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2. Miller, Charles A., Bi-directional buffer for interfacing test system channel.

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3. Rathburn, James, Bumped semiconductor wafer or die level electrical interconnect.

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4. Rathburn, James, Compliant printed circuit area array semiconductor device package.

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5. Rathburn, James, Compliant printed circuit semiconductor package.

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6. Rathburn, James, Compliant printed circuit semiconductor tester interface.

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7. Rathburn, James, Compliant printed circuit socket diagnostic tool.

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8. Rathburn, James, Compliant printed circuit wafer level semiconductor package.

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9. Rathburn, James, Compliant printed circuit wafer probe diagnostic tool.

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10. Rathburn, James, Compliant printed flexible circuit.

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11. Rathburn, James, Composite polymer-metal electrical contacts.

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12. Rathburn, Jim, Copper pillar full metal via electrical circuit structure.

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13. Rathburn, James, Direct metalization of electrical circuit structures.

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14. Rathburn, James, Electrical connector insulator housing.

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15. Rathburn, James, Electrical interconnect IC device socket.

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16. Rathburn, James, Electrical interconnect IC device socket.

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17. Rathburn, James, Fusion bonded liquid crystal polymer circuit structure.

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18. Rathburn, James, High performance electrical circuit structure.

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19. Rathburn, James, High performance surface mount electrical interconnect.

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20. Rathburn, James, High performance surface mount electrical interconnect.

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21. Rathburn, James, High performance surface mount electrical interconnect.

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22. Rathburn, James, High performance surface mount electrical interconnect with external biased normal force loading.

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23. Rathburn, James, High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly.

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24. Rathburn, James, Hybrid printed circuit assembly with low density main core and embedded high density circuit regions.

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25. Rathburn, James J., Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction.

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26. Rathburn, James J., Mechanical contact retention within an electrical connector.

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27. Rathburn, James, Metalized pad to electrical contact interface.

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28. Rathburn, James, Method of forming a semiconductor socket.

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29. Rathburn, James J., Method of making an electrical connector having electrodeposited terminals.

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30. Rathburn, Jim, Method of making an electronic interconnect.

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31. Rathburn, James, Performance enhanced semiconductor socket.

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32. Rathburn, James, Resilient conductive electrical interconnect.

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33. Rathburn, Jim, Selective metalization of electrical connector or socket housing.

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34. Rathburn, James, Semiconductor device package adapter.

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35. Rathburn, James, Semiconductor die terminal.

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36. Rathburn, James, Semiconductor socket with direct selective metalization.

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37. Rathburn, James, Singulated semiconductor device separable electrical interconnect.

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