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Non-volatile memory and method with reduced source line bias errors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-016/06
출원번호 US-0254830 (2002-09-24)
발명자 / 주소
  • Cernea,Raul Adrian
  • Li,Yan
출원인 / 주소
  • SanDisk Corporation
대리인 / 주소
    Parsons Hsue & de Runtz LLP
인용정보 피인용 횟수 : 59  인용 특허 : 49

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (49)

  1. Maayan, Eduardo; Sofer, Yair; Eliyahu, Ron; Eitan, Boaz, Architecture and scheme for a non-strobed read sequence.
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  2. Yamamoto, Kaoru; Ito, Nobuhiko, BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH THE DECODER CIRCUIT, AND DATA READ METHOD OF VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR.
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  3. Kim, Dae Han, Circuit for clamping word-line voltage.
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  4. Yuan Jack H. (Cupertino CA) Samachisa Gheorghe (San Jose CA) Guterman Daniel C. (Fremont CA) Harari Eliyahou (Los Gatos CA), Dense vertical programmable read only memory cell structure and processes for making them.
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  5. Parker Allan, Descending staircase read technique for a multilevel cell NAND flash memory device.
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  6. Young Kenneth E. (Newark CA), Differential bit line clamp.
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  7. Hollmer, Shane C.; Chen, Pau-Ling; Binh, Quang, Double boosting scheme for NAND to improve program inhibit characteristics.
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  8. Hultberg Kent,SEX ; Ranta Teuvo,SEX ; Larsson Hans,SEX, Double-walled structure in a ventilation duct system.
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  9. Guterman Daniel C. (Fremont CA) Samachisa Gheorghe (San Jose CA) Fong Yupin K. (Fremont CA) Harrai Eliyahou (Los Gatos CA), EEPROM with split gate source side injection.
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  10. Gongwer, Geoffrey S., Efficient read, write methods for multi-state memory.
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  11. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash EEPROM system with erase sector select.
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  12. Harari Eliyahou (2320 Friars La. Los Altos CA 94022), Highly compact EPROM and flash EEPROM devices.
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  13. Tsao, Cheng-Chung; Lin, Tien-ler, Integrated circuit memory device having interleaved read and program capabilities and methods of operating same.
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  14. James M. Cleeves, Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays.
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  15. Wong, Sau Ching, Memory with offset bank select cells at opposite ends of buried diffusion lines.
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  16. Smith Kevin B. ; Garvin P. Keith, Method and apparatus for allocating storage in a flash memory.
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  17. Beer, Peter, Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory.
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  18. Choi Jung-Dal,KRX, Method for programming a non-volatile memory device with program disturb control.
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  19. Yuan Jack H. (Cupertino CA), Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with t.
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  20. Yuan Jack H. (Cupertino CA) Harari Eliyahou (Los Gatos CA), Method of making dense flash EEprom semiconductor memory structures.
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  21. Daniele Vincenzo (Milan ITX) Corda Giuseppe (Saronno ITX) Magrucci Aldo (Milan ITX) Torelli Guido (Milan ITX), Method of programming an electrically alterable nonvolatile memory.
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  22. Mangan, John S.; Guterman, Daniel C.; Samachisa, George; Murphy, Brian; Wang, Chi-Ming; Quader, Khandker N., Method of reducing disturbs in non-volatile memory.
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  23. Tanaka Tomoharu (Yokohama JPX) Hemink Gertjan (Kawasaki JPX), Multi-state EEPROM having write-verify control circuit.
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  24. Mehrotra Sanjay (Milpitas CA) Harari Eliyahou (Los Gatos CA) Lee Winston (San Francisco CA), Multi-state EEprom read and write circuits and techniques.
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  25. Guterman Daniel C. ; Fong Yupin Kawing, Multi-state memory.
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  26. Khalid, Shahzad; Li, Yan; Cernea, Raul-Adrian; Mofidi, Mehrdad, Non-volatile memory and method with bit line compensation dependent on neighboring operating modes.
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  27. Cernea,Raul Adrian; Li,Yan, Non-volatile memory and method with improved sensing.
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  28. Eitan Boaz,ILX, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping.
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  29. Itoh Yasuo,JPX ; Sakui Koji,JPX, Non-volatile semiconductor memory device.
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  30. Endoh Tetsuo,JPX ; Tanaka Yoshiyuki,JPX ; Aritome Seiichi,JPX ; Shirota Riichiro,JPX ; Shuto Susumu,JPX ; Tanaka Tomoharu,JPX ; Hemink Gertjan,JPX ; Tanzawa Toru,JPX, Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state.
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  31. Akaogi Takao (Kawasaki JPX) Yoshida Masanobu (Kawasaki JPX) Oqawa Yasushige (Kasuqai JPX) Kasa Yasushi (Kawasaki JPX) Kawamura Shouichi (Kawasaki JPX), Nonvolatile semiconductor memory.
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  32. Takeuchi Ken,JPX ; Sakui Koji,JPX ; Tanaka Tomoharu,JPX ; Aritome Seiichi,JPX, Nonvolatile semiconductor memory device.
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  33. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Nonvolatile semiconductor memory device.
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  34. Satoh Shinji,JPX ; Shirota Riichiro,JPX ; Tanzawa Toru,JPX, Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse.
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  35. Ken Takeuchi JP; Tomoharu Tanaka JP; Noboru Shibata JP, Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells.
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  36. Noda Masanori,JPX ; Arase Kenshiro,JPX ; Sugiyama Toshinobu,JPX ; Naiki Ihachi,JPX, Nonvolatile semiconductor memory with fast data programming and erasing function using ECC.
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  37. Harari Eliyahou (Los Gatos CA) Mehrotra Sanjay (Milpitas CA), Segmented column memory array.
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  38. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Semiconductor device and memory system.
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  39. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Semiconductor device and memory system.
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  40. Himeno Toshihiko,JPX ; Kanda Kazushige,JPX ; Nakamura Hiroshi,JPX, Semiconductor memory device.
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  41. Byeong-Hoon Lee KR; Young-Ho Lim KR, Sense amplifier circuit for a flash memory device.
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  42. Takahashi Hiroyuki (Tokyo JPX), Sense amplifier circuit implemented by bipolar transistor and improved in current consumption.
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  43. Womack Richard, Sense amplifier for low read-voltage memory cells.
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  44. Tran Hiep V. (1816 Woodbury Carrollton TX 75007), Sensing and decoding scheme for a BiCMOS read/write memory.
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  45. Yuan Jack H. (Cupertino CA) Samachisa Gheorghe (San Jose CA), Technique of forming over an irregular surface a polysilicon layer with a smooth surface.
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  46. Eitan Boaz,ILX, Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
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  47. Brady James, Voltage clamping method and apparatus for dynamic random access memory devices.
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  48. Shaw Jeng-Jye, Wrap-around mechanism for memory split-wordline read.
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  49. Kai Yasuyuki (Yokohama JPX), semiconductor memory device having a flash write function.
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이 특허를 인용한 특허 (59)

  1. Sel, Jong Sun; Gunji-Yoneoka, Marika; Takeguchi, Naoki; Park, Chan; Pham, Tuan D.; Tokunaga, Kazuya, Air gap formation between bit lines with side protection.
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  2. Sel, Jong Sun; Gunji-Yoneoka, Marika; Takeguchi, Naoki; Park, Chan; Pham, Tuan D.; Tokunaga, Kazuya, Air gap formation between bit lines with top protection.
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  3. Li, Yan, Alternate page by page programming scheme.
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  4. Li, Yan, Compensating for coupling during programming.
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  5. Li, Yan Li, Compensating for coupling during programming.
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  6. Dutta, Deepanshu; Lutze, Jeffrey W., Compensating non-volatile storage using different pass voltages during program-verify and read.
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  7. Sekar, Deepak Chandra; Mokhlesi, Nima; Nguyen, Hao Thai; Lee, Seungpil; Mui, Man Lung, Compensating source voltage drop in non-volatile storage.
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  8. Mokhlesi, Nima, Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution.
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  9. Mokhlesi, Nima, Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution.
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  10. Mokhlesi, Nima, Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution.
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  11. Dong, Yingda; Mui, Man L.; Lutze, Jeffrey W.; Sato, Shinji; Hemink, Gerrit Jan, Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage.
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  12. Hemink, Gerrit Jan, Faster programming of multi-level non-volatile storage through reduced verify operations.
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  13. Lasser, Menahem, Flash memory with improved programming precision.
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  14. Chan, Siu Lung; Cernea, Raul Adrian, Method for compensated sensing in non-volatile memory.
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  15. Li, Yan; Lin, Jason, Method for non-volatile memory with background data latch caching during erase operations.
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  16. Li,Yan, Method for non-volatile memory with background data latch caching during program operations.
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  17. Li, Yan, Method for non-volatile memory with background data latch caching during read operations.
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  18. Li, Yan, Method for non-volatile memory with background data latch caching during read operations.
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  19. Li, Yan, Method for non-volatile memory with background data latch caching during read operations.
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  20. Li,Yan, Method for non-volatile memory with background data latch caching during read operations.
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  21. Li,Yan, Method for non-volatile memory with managed execution of cached data.
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  22. Lasser, Menahem, Method of improving programming precision in flash memory.
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  23. Miwa, Toru; Hemink, Gerrit Jan, Multi-pass programming for memory with reduced data storage requirement.
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  24. Li, Yan, Non-volatile memory and method for biasing adjacent word line for verify during programming.
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  25. Cernea,Raul Adrian; Li,Yan, Non-volatile memory and method with improved sensing.
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  26. Mokhlesi, Nima, Non-volatile memory and method with improved sensing having a bit-line lockout control.
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  27. Mokhlesi, Nima, Non-volatile memory and method with improved sensing having bit-line lockout control.
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  28. Mokhlesi, Nima, Non-volatile memory and method with improved sensing having bit-line lockout control.
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  29. Cernea, Raul Adrian; Li, Yan, Non-volatile memory and method with reduced source line bias errors.
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  30. Li, Yan; Lin, Jason, Non-volatile memory with background data latch caching during erase operations.
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  31. Li,Yan, Non-volatile memory with background data latch caching during program operations.
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  32. Li,Yan, Non-volatile memory with background data latch caching during read operations.
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  33. Cernea, Raul-Adrian, Non-volatile memory with improved sensing by reducing source line current.
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  34. Cernea, Raul-Adrian, Non-volatile memory with improved sensing by reducing source line current.
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  35. Cernea, Raul-Adrian, Non-volatile memory with improved sensing by reducing source line current.
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  36. Mokhlesi,Nima, Non-volatile memory with improved sensing having bit-line lockout control.
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  37. Li,Yan, Non-volatile memory with managed execution of cached data.
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  38. Sekar, Deepak Chandra; Mokhlesi, Nima; Nguyen, Hao Thai; Lee, Seungpil; Mui, Man Lung, Non-volatile storage with compensation for source voltage drop.
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  39. Li, Yan, Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells.
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  40. Tanaka, Toshihiro; Yamaki, Takashi; Shinagawa, Yutaka; Okada, Daisuke; Hisamoto, Digh; Yasui, Kan; Ishimaru, Tetsuya, Nonvolatile memory device and semiconductor device.
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  41. Murin, Mark; Shlick, Mark; Lasser, Menahem; Trinh, Cuong, Operation sequence and commands for measuring threshold voltage distribution in memory.
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  42. Lee, Dana; Dutta, Deepanshu; Dong, Yingda, Programming algorithm to reduce disturb with minimal extra time penalty.
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  43. Lee, Dana; Wan, Jun, Reducing programming voltage differential nonlinearity in non-volatile storage.
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  44. Fong,Yupin; Wan,Jun; Lutze,Jeffrey, Reducing read disturb for non-volatile storage.
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  45. Fong,Yupin; Wan,Jun; Lutze,Jeffrey, Reducing read disturb for non-volatile storage.
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  46. Fong,Yupin; Wan,Jun; Lutze,Jeffrey, Reducing read disturb for non-volatile storage.
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  47. Maeda, Takashi, Semiconductor memory device controlling operation timing of the sense circuit.
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  48. Maeda, Takashi, Semiconductor storage device.
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  49. Nguyen, Hao Thai; Mui, Man Lung; Lee, Seungpil; Wang, Chi Ming, Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise.
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  50. Mokhlesi,Nima, Sensing with bit-line lockout control in non-volatile memory.
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  51. Dong, Yingda; Lutze, Jeffrey W., Source and drain side early boosting using local self boosting for non-volatile storage.
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  52. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
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  53. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
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  54. Li, Yan; Fong, Yupin, System that compensates for coupling based on sensing a neighbor using coupling.
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  55. Li, Yan, System that compensates for coupling during programming.
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  56. Li,Yan, System that compensates for coupling during programming.
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  57. Jeyasingh, Rakesh; Gajera, Nevil N.; Taub, Mase J.; Pangal, Kiran, Techniques to mitigate bias drift for a memory device.
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  58. Li, Yan; Yero, Emilio, Use of data latches in cache operations of non-volatile memories.
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  59. Li,Yan; Cernea,Raul Adrian, Use of data latches in multi-phase programming of non-volatile memories.
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