이 특허에 인용된 특허 (63) 인용/피인용 타임라인 분석

1. Makoto Terui JP, BGA package and method for fabricating the same.

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2. Akram, Salman, Chip package with grease heat sink.

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3. Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.

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4. Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.

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5. Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.

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6. Song, Young-Jae; Kwon, Young-Shin; Youm, Kun-Dae; Kim, Young-Soo, Higher-density memory card.

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7. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.

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8. Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.

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9. Maeda, Takehiko; Tsukano, Jun, Light thin stacked package semiconductor device and process for fabrication thereof.

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10. Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.

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11. Koopmans, Michel, Method of fabricating stacked die configurations utilizing redistribution bond pads.

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12. Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.

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13. Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.

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14. Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.

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15. Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.

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16. Liu,Cheng Cheng, Multi-chip package combining wire-bonding and flip-chip configuration.

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17. Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.

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18. Hsu, Chi-Hsing, Quad flat no-lead chip carrier.

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19. Uchida, Yasufumi; Saeki, Yoshihiro, Rearrangement sheet, semiconductor device and method of manufacturing thereof.

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20. Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.

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21. Ichinose, Michihiko; Takizawa, Tomoko; Honda, Hirokazu; Kata, Keiichirou, Resin-encapsulated semiconductor device.

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22. Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.

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23. Ichikawa, Sunji, Semiconductor device.

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24. Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.

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25. Tadashi Komiyama JP, Semiconductor device.

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26. Terui, Makoto, Semiconductor device.

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27. Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.

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28. Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.

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29. Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.

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30. Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.

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31. Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.

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32. Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.

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33. Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.

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34. Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.

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35. Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.

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36. Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.

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37. Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.

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38. Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.

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39. Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.

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40. Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.

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41. Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.

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42. Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.

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43. De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.

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44. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.

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45. Tao Su,TWX ; Lo Kuang-Lin,TWX ; Chou Kuang-Chun,TWX ; Chen Shih-Chih,TWX, Stacked chip assembly utilizing a lead frame.

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46. McMahon, John F., Stacked chip packaging.

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47. Akram Salman, Stacked leads-over chip multi-chip module.

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48. Mess, Leonard E.; Brooks, Jerry M.; Corisis, David J., Stacked mass storage flash memory package.

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49. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.

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50. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.

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51. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.

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52. St. Amand, Roger D.; Perelman, Vladimir, Stacked semiconductor die assembly having at least one support.

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53. Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.

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54. St. Amand,Roger D.; Kim,InTae; Perelman,Vladimir, Stacked-die extension support structure and method thereof.

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55. Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.

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56. Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.

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57. Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.

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58. Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.

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59. Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.

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60. Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.

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61. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.

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62. Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.

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63. Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.

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이 특허를 인용한 특허 (26) 인용/피인용 타임라인 분석

1. Liu, Yong; Qian, Qiuxiao, Embedded die package on package (POP) with pre-molded leadframe.

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2. Liu, Yong; Qian, Qiuxiao, Embedded die package on package (POP) with pre-molded leadframe.

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3. Chow, Seng Guan; Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati, Integrated circuit package system with flexible substrate and mounded package.

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4. Chow, Seng Guan; Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati, Integrated circuit package system with flexible substrate and recessed package.

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5. Chow, Seng Guan; Kuan, Heap Hoe; Pagaila, Reza Argenty, Integrated circuit package system with internal stacking module.

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6. Chow, Seng Guan; Kuan, Heap Hoe; Pagaila, Reza Argenty, Integrated circuit package system with internal stacking module.

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7. Ha, Jong-Woo; Hong, BumJoon; Lee, Sang-Ho; Park, Soo-San, Integrated circuit package-in-package system with carrier interposer.

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8. Karnezos, Marcos, Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages.

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9. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.

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10. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.

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11. Woodyard, Jon T., Package in package (PiP).

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12. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.

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18. Onodera, Masanori, Semiconductor device and method of manufacturing the same.

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20. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.

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21. Karnezos, Marcos, Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array package.

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